From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
To: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
bhelgaas@google.com, jingoohan1@gmail.com,
gustavo.pimentel@synopsys.com
Cc: Sergey.Semin@baikalelectronics.ru, marek.vasut+renesas@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org,
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Subject: [PATCH v10 05/12] PCI: dwc: Refactor PCIE_PORT_LINK_CONTROL handling
Date: Wed, 8 Mar 2023 17:23:45 +0900 [thread overview]
Message-ID: <20230308082352.491561-6-yoshihiro.shimoda.uh@renesas.com> (raw)
In-Reply-To: <20230308082352.491561-1-yoshihiro.shimoda.uh@renesas.com>
The previous code wrote this PCIE_PORT_LINK_CONTROL register twice
with redudant mask (PORT_LINK_FAST_LINK_MODE). So, refactor this.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
drivers/pci/controller/dwc/pcie-designware.c | 20 ++++++++------------
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 8e33e6e59e68..89b8ec29da7f 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -1008,19 +1008,13 @@ void dw_pcie_setup(struct dw_pcie *pci)
dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
}
+ /* Set the number of lanes */
val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
val &= ~PORT_LINK_FAST_LINK_MODE;
val |= PORT_LINK_DLL_LINK_EN;
- dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
-
- if (!pci->num_lanes) {
- dev_dbg(pci->dev, "Using h/w default number of lanes\n");
- return;
- }
-
- /* Set the number of lanes */
- val &= ~PORT_LINK_FAST_LINK_MODE;
- val &= ~PORT_LINK_MODE_MASK;
+ /* Mask LINK_MODE if num_lanes is not zero */
+ if (pci->num_lanes)
+ val &= ~PORT_LINK_MODE_MASK;
switch (pci->num_lanes) {
case 1:
val |= PORT_LINK_MODE_1_LANES;
@@ -1035,10 +1029,12 @@ void dw_pcie_setup(struct dw_pcie *pci)
val |= PORT_LINK_MODE_8_LANES;
break;
default:
- dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->num_lanes);
- return;
+ dev_dbg(pci->dev, "Using h/w default number of lanes\n");
+ break;
}
dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
+ if (!pci->num_lanes)
+ return;
/* Set link width speed control register */
val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
--
2.25.1
next prev parent reply other threads:[~2023-03-08 8:25 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-08 8:23 [PATCH v10 00/12] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
2023-03-08 8:23 ` [PATCH v10 01/12] PCI: dwc: Fix writing wrong value if snps,enable-cdm-check Yoshihiro Shimoda
2023-03-08 8:23 ` [PATCH v10 02/12] PCI: endpoint: functions/pci-epf-test: Fix dma_chan direction Yoshihiro Shimoda
2023-03-08 8:23 ` [PATCH v10 03/12] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host Yoshihiro Shimoda
2023-03-08 8:23 ` [PATCH v10 04/12] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint Yoshihiro Shimoda
2023-03-08 14:06 ` Rob Herring
2023-03-08 8:23 ` Yoshihiro Shimoda [this message]
2023-03-08 8:23 ` [PATCH v10 06/12] PCI: Add PCI_EXP_LNKCAP_MLW macros Yoshihiro Shimoda
2023-03-08 8:23 ` [PATCH v10 07/12] PCI: designware-ep: Expose dw_pcie_ep_exit() to module Yoshihiro Shimoda
2023-03-08 8:23 ` [PATCH v10 08/12] PCI: dwc: Add dw_pcie_num_lanes_setup() Yoshihiro Shimoda
2023-03-08 8:23 ` [PATCH v10 09/12] PCI: dwc: Add support for triggering legacy IRQs Yoshihiro Shimoda
2023-03-08 8:23 ` [PATCH v10 10/12] PCI: rcar-gen4: Add R-Car Gen4 PCIe Host support Yoshihiro Shimoda
2023-03-08 8:23 ` [PATCH v10 11/12] PCI: rcar-gen4-ep: Add R-Car Gen4 PCIe Endpoint support Yoshihiro Shimoda
2023-03-08 8:23 ` [PATCH v10 12/12] MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4 Yoshihiro Shimoda
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