From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org,
kw@linux.com, krzysztof.kozlowski+dt@linaro.org,
vkoul@kernel.org
Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org,
linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: [PATCH v3 12/13] phy: qcom-qmp-pcie: Add RC init sequence for SDX55
Date: Wed, 8 Mar 2023 13:54:23 +0530 [thread overview]
Message-ID: <20230308082424.140224-13-manivannan.sadhasivam@linaro.org> (raw)
In-Reply-To: <20230308082424.140224-1-manivannan.sadhasivam@linaro.org>
Add PCIe RC init sequence making use of the common init sequence. The RC
mode additionally requires REFCLK_DRV_DSBL bit to set during powerup and
powerdown.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 49 ++++++++++++++++++-
.../qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h | 2 +
2 files changed, 50 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 35328e998699..d671748bc097 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -1146,6 +1146,41 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
};
+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xce),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x0b),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x97),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE0, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE1, 0x10),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0d),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0xc3),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0xd0),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0x55),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0x55),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xd8),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x20),
+};
+
static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
@@ -1225,6 +1260,11 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
};
+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_pcs_misc_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
+};
+
static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_misc_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
@@ -2308,6 +2348,13 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
.pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
},
+ .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
+ .serdes = sdx55_qmp_pcie_rc_serdes_tbl,
+ .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_serdes_tbl),
+ .pcs_misc = sdx55_qmp_pcie_rc_pcs_misc_tbl,
+ .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_pcs_misc_tbl),
+ },
+
.tbls_ep = &(const struct qmp_phy_cfg_tbls) {
.serdes = sdx55_qmp_pcie_ep_serdes_tbl,
.serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl),
@@ -2323,7 +2370,7 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
.regs = pciephy_v4_regs_layout,
- .pwrdn_ctrl = SW_PWRDN,
+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
.phy_status = PHYSTATUS_4_20,
};
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h
index af273602998e..ac872a9eff9a 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h
@@ -6,6 +6,8 @@
#ifndef QCOM_PHY_QMP_PCS_PCIE_V4_20_H_
#define QCOM_PHY_QMP_PCS_PCIE_V4_20_H_
+#define QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
+#define QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0
#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0
#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4
--
2.25.1
next prev parent reply other threads:[~2023-03-08 8:27 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-08 8:24 [PATCH v3 00/13] Add PCIe RC support to Qcom SDX55 SoC Manivannan Sadhasivam
2023-03-08 8:24 ` [PATCH v3 01/13] dt-bindings: PCI: qcom: Update maintainers entry Manivannan Sadhasivam
2023-03-08 8:24 ` [PATCH v3 02/13] dt-bindings: PCI: qcom: Add iommu-map properties Manivannan Sadhasivam
2023-03-16 22:51 ` Rob Herring
2023-03-08 8:24 ` [PATCH v3 03/13] dt-bindings: PCI: qcom: Add SDX55 SoC Manivannan Sadhasivam
2023-03-08 8:24 ` [PATCH v3 04/13] dt-bindings: PCI: qcom-ep: Fix the unit address used in example Manivannan Sadhasivam
2023-03-08 8:24 ` [PATCH v3 05/13] ARM: dts: qcom: sdx55: Fix the unit address of PCIe EP node Manivannan Sadhasivam
2023-03-08 8:24 ` [PATCH v3 06/13] ARM: dts: qcom: sdx55: Rename pcie0_{phy/lane} to pcie_{phy/lane} Manivannan Sadhasivam
2023-03-08 8:24 ` [PATCH v3 07/13] ARM: dts: qcom: sdx55: Add support for PCIe RC controller Manivannan Sadhasivam
2023-03-08 8:24 ` [PATCH v3 08/13] ARM: dts: qcom: sdx55: List the property values vertically Manivannan Sadhasivam
2023-03-08 8:24 ` [PATCH v3 09/13] ARM: dts: qcom: sdx55-t55: Enable PCIe RC support Manivannan Sadhasivam
2023-03-08 8:24 ` [PATCH v3 10/13] ARM: dts: qcom: sdx55-t55: Move "status" property down Manivannan Sadhasivam
2023-03-08 8:24 ` [PATCH v3 11/13] phy: qcom-qmp-pcie: Split out EP related init sequence for SDX55 Manivannan Sadhasivam
2023-03-20 9:27 ` Vinod Koul
2023-03-08 8:24 ` Manivannan Sadhasivam [this message]
2023-03-20 9:27 ` [PATCH v3 12/13] phy: qcom-qmp-pcie: Add RC " Vinod Koul
2023-03-08 8:24 ` [PATCH v3 13/13] PCI: qcom: Add support for SDX55 SoC Manivannan Sadhasivam
2023-03-16 3:20 ` (subset) [PATCH v3 00/13] Add PCIe RC support to Qcom " Bjorn Andersson
2023-04-11 10:09 ` Lorenzo Pieralisi
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