From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com,
krzysztof.kozlowski+dt@linaro.org, robh@kernel.org
Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, quic_srichara@quicinc.com,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: [PATCH v2 16/17] arm64: dts: qcom: sc8280xp: Add "mhi" region to the PCIe nodes
Date: Thu, 9 Mar 2023 14:21:01 +0530 [thread overview]
Message-ID: <20230309085102.120977-17-manivannan.sadhasivam@linaro.org> (raw)
In-Reply-To: <20230309085102.120977-1-manivannan.sadhasivam@linaro.org>
The "mhi" region contains the debug registers that could be used to monitor
the PCIe link transitions.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 25 +++++++++++++++----------
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 0d02599d8867..eb87c3e5d2bc 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -1653,8 +1653,9 @@ pcie4: pcie@1c00000 {
<0x0 0x30000000 0x0 0xf1d>,
<0x0 0x30000f20 0x0 0xa8>,
<0x0 0x30001000 0x0 0x1000>,
- <0x0 0x30100000 0x0 0x100000>;
- reg-names = "parf", "dbi", "elbi", "atu", "config";
+ <0x0 0x30100000 0x0 0x100000>,
+ <0x0 0x01c03000 0x0 0x1000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x30200000 0x0 0x30200000 0x0 0x100000>,
@@ -1752,8 +1753,9 @@ pcie3b: pcie@1c08000 {
<0x0 0x32000000 0x0 0xf1d>,
<0x0 0x32000f20 0x0 0xa8>,
<0x0 0x32001000 0x0 0x1000>,
- <0x0 0x32100000 0x0 0x100000>;
- reg-names = "parf", "dbi", "elbi", "atu", "config";
+ <0x0 0x32100000 0x0 0x100000>,
+ <0x0 0x01c0b000 0x0 0x1000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x32200000 0x0 0x32200000 0x0 0x100000>,
@@ -1849,8 +1851,9 @@ pcie3a: pcie@1c10000 {
<0x0 0x34000000 0x0 0xf1d>,
<0x0 0x34000f20 0x0 0xa8>,
<0x0 0x34001000 0x0 0x1000>,
- <0x0 0x34100000 0x0 0x100000>;
- reg-names = "parf", "dbi", "elbi", "atu", "config";
+ <0x0 0x34100000 0x0 0x100000>,
+ <0x0 0x01c13000 0x0 0x1000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x34200000 0x0 0x34200000 0x0 0x100000>,
@@ -1949,8 +1952,9 @@ pcie2b: pcie@1c18000 {
<0x0 0x38000000 0x0 0xf1d>,
<0x0 0x38000f20 0x0 0xa8>,
<0x0 0x38001000 0x0 0x1000>,
- <0x0 0x38100000 0x0 0x100000>;
- reg-names = "parf", "dbi", "elbi", "atu", "config";
+ <0x0 0x38100000 0x0 0x100000>,
+ <0x0 0x01c1b000 0x0 0x1000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x38200000 0x0 0x38200000 0x0 0x100000>,
@@ -2046,8 +2050,9 @@ pcie2a: pcie@1c20000 {
<0x0 0x3c000000 0x0 0xf1d>,
<0x0 0x3c000f20 0x0 0xa8>,
<0x0 0x3c001000 0x0 0x1000>,
- <0x0 0x3c100000 0x0 0x100000>;
- reg-names = "parf", "dbi", "elbi", "atu", "config";
+ <0x0 0x3c100000 0x0 0x100000>,
+ <0x0 0x01c23000 0x0 0x1000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>,
--
2.25.1
next prev parent reply other threads:[~2023-03-09 8:53 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-09 8:50 [PATCH v2 00/17] Qcom PCIe cleanups and improvements Manivannan Sadhasivam
2023-03-09 8:50 ` [PATCH v2 01/17] PCI: qcom: Remove PCIE20_ prefix from register definitions Manivannan Sadhasivam
2023-03-09 8:50 ` [PATCH v2 02/17] PCI: qcom: Sort and group registers and bitfield definitions Manivannan Sadhasivam
2023-03-09 8:50 ` [PATCH v2 03/17] PCI: qcom: Use bitfield definitions for register fields Manivannan Sadhasivam
2023-03-09 8:50 ` [PATCH v2 04/17] PCI: qcom: Add missing macros " Manivannan Sadhasivam
2023-03-09 8:50 ` [PATCH v2 05/17] PCI: qcom: Use lower case for hex Manivannan Sadhasivam
2023-03-09 8:50 ` [PATCH v2 06/17] PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.1.0 Manivannan Sadhasivam
2023-03-09 8:50 ` [PATCH v2 07/17] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 1.0.0 Manivannan Sadhasivam
2023-03-09 8:50 ` [PATCH v2 08/17] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.2 Manivannan Sadhasivam
2023-03-09 8:50 ` [PATCH v2 09/17] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.3 Manivannan Sadhasivam
2023-03-09 8:50 ` [PATCH v2 10/17] PCI: qcom: Use bulk reset APIs for handling resets " Manivannan Sadhasivam
2023-03-09 8:50 ` [PATCH v2 11/17] PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.4.0 Manivannan Sadhasivam
2023-03-09 8:50 ` [PATCH v2 12/17] PCI: qcom: Use macros for defining total no. of clocks & supplies Manivannan Sadhasivam
2023-03-09 8:50 ` [PATCH v2 13/17] dt-bindings: PCI: qcom: Add "mhi" register region to supported SoCs Manivannan Sadhasivam
2023-03-09 8:50 ` [PATCH v2 14/17] arm64: dts: qcom: sdm845: Add "mhi" region to the PCIe nodes Manivannan Sadhasivam
2023-03-09 8:51 ` [PATCH v2 15/17] arm64: dts: qcom: sm8250: " Manivannan Sadhasivam
2023-03-09 8:51 ` Manivannan Sadhasivam [this message]
2023-03-09 8:51 ` [PATCH v2 17/17] PCI: qcom: Expose link transition counts via debugfs Manivannan Sadhasivam
2023-03-09 11:51 ` Sricharan Ramabadhran
2023-03-09 14:53 ` Manivannan Sadhasivam
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230309085102.120977-17-manivannan.sadhasivam@linaro.org \
--to=manivannan.sadhasivam@linaro.org \
--cc=andersson@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=konrad.dybcio@linaro.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=kw@linux.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lpieralisi@kernel.org \
--cc=quic_srichara@quicinc.com \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).