From: Rick Wertenbroek <rick.wertenbroek@gmail.com>
To: alberto.dassatti@heig-vd.ch
Cc: damien.lemoal@opensource.wdc.com, xxm@rock-chips.com,
"Rick Wertenbroek" <rick.wertenbroek@gmail.com>,
stable@vger.kernel.org, "Shawn Lin" <shawn.lin@rock-chips.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Heiko Stuebner" <heiko@sntech.de>,
"Johan Jonker" <jbx6244@gmail.com>,
"Brian Norris" <briannorris@chromium.org>,
"Caleb Connolly" <kc@postmarketos.org>,
"Corentin Labbe" <clabbe@baylibre.com>,
"Sascha Hauer" <s.hauer@pengutronix.de>,
"Judy Hsiao" <judyhsiao@chromium.org>,
"Lin Huang" <hl@rock-chips.com>,
"Arnaud Ferraris" <arnaud.ferraris@collabora.com>,
"Hugh Cole-Baker" <sigmaris@gmail.com>,
linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v3 09/11] PCI: rockchip: Use u32 variable to access 32-bit registers
Date: Tue, 4 Apr 2023 10:24:22 +0200 [thread overview]
Message-ID: <20230404082426.3880812-10-rick.wertenbroek@gmail.com> (raw)
In-Reply-To: <20230404082426.3880812-1-rick.wertenbroek@gmail.com>
Previously u16 variables were used to access 32-bit registers, this
resulted in not all of the data being read from the registers. Also
the left shift of more than 16-bits would result in moving data out
of the variable. Use u32 variables to access 32-bit registers
Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller")
Cc: stable@vger.kernel.org
Signed-off-by: Rick Wertenbroek <rick.wertenbroek@gmail.com>
---
drivers/pci/controller/pcie-rockchip-ep.c | 10 +++++-----
drivers/pci/controller/pcie-rockchip.h | 1 +
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c
index f366846ad77c..924b95bd736c 100644
--- a/drivers/pci/controller/pcie-rockchip-ep.c
+++ b/drivers/pci/controller/pcie-rockchip-ep.c
@@ -274,15 +274,15 @@ static int rockchip_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn,
{
struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
struct rockchip_pcie *rockchip = &ep->rockchip;
- u16 flags;
+ u32 flags;
flags = rockchip_pcie_read(rockchip,
ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK;
flags |=
- ((multi_msg_cap << 1) << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) |
- PCI_MSI_FLAGS_64BIT;
+ (multi_msg_cap << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) |
+ (PCI_MSI_FLAGS_64BIT << ROCKCHIP_PCIE_EP_MSI_FLAGS_OFFSET);
flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP;
rockchip_pcie_write(rockchip, flags,
ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
@@ -294,7 +294,7 @@ static int rockchip_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn)
{
struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
struct rockchip_pcie *rockchip = &ep->rockchip;
- u16 flags;
+ u32 flags;
flags = rockchip_pcie_read(rockchip,
ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
@@ -355,7 +355,7 @@ static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn,
u8 interrupt_num)
{
struct rockchip_pcie *rockchip = &ep->rockchip;
- u16 flags, mme, data, data_mask;
+ u32 flags, mme, data, data_mask;
u8 msi_count;
u64 pci_addr, pci_addr_mask = 0xff;
u32 r;
diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h
index 5797ba73bb6b..1558eae298ae 100644
--- a/drivers/pci/controller/pcie-rockchip.h
+++ b/drivers/pci/controller/pcie-rockchip.h
@@ -226,6 +226,7 @@
#define ROCKCHIP_PCIE_EP_CMD_STATUS 0x4
#define ROCKCHIP_PCIE_EP_CMD_STATUS_IS BIT(19)
#define ROCKCHIP_PCIE_EP_MSI_CTRL_REG 0x90
+#define ROCKCHIP_PCIE_EP_MSI_FLAGS_OFFSET 16
#define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET 17
#define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK GENMASK(19, 17)
#define ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET 20
--
2.25.1
next prev parent reply other threads:[~2023-04-04 8:26 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-04 8:24 [PATCH v3 00/11] PCI: rockchip: Fix RK3399 PCIe endpoint controller driver Rick Wertenbroek
2023-04-04 8:24 ` [PATCH v3 01/11] PCI: rockchip: Remove writes to unused registers Rick Wertenbroek
2023-04-04 8:24 ` [PATCH v3 02/11] PCI: rockchip: Write PCI Device ID to correct register Rick Wertenbroek
2023-04-04 8:24 ` [PATCH v3 03/11] PCI: rockchip: Assert PCI Configuration Enable bit after probe Rick Wertenbroek
2023-04-04 8:24 ` [PATCH v3 04/11] PCI: rockchip: Add poll and timeout to wait for PHY PLLs to be locked Rick Wertenbroek
2023-04-04 8:24 ` [PATCH v3 05/11] arm64: dts: rockchip: Add dtsi entry for RK3399 PCIe endpoint core Rick Wertenbroek
2023-04-04 8:24 ` [PATCH v3 06/11] dt-bindings: PCI: Update the RK3399 example to a valid one Rick Wertenbroek
2023-04-04 8:45 ` Krzysztof Kozlowski
2023-04-04 8:58 ` Rick Wertenbroek
2023-04-04 13:29 ` Krzysztof Kozlowski
2023-04-04 14:42 ` Rick Wertenbroek
2023-04-04 8:24 ` [PATCH v3 07/11] PCI: rockchip: Fix legacy IRQ generation for RK3399 PCIe endpoint core Rick Wertenbroek
2023-04-04 8:24 ` [PATCH v3 08/11] PCI: rockchip: Fix window mapping and address translation for endpoint Rick Wertenbroek
2023-04-05 11:43 ` Damien Le Moal
2023-04-04 8:24 ` Rick Wertenbroek [this message]
2023-04-04 8:24 ` [PATCH v3 10/11] PCI: rockchip: Don't advertise MSI-X in PCIe capabilities Rick Wertenbroek
2023-04-05 11:50 ` Damien Le Moal
2023-04-04 8:24 ` [PATCH v3 11/11] PCI: rockchip: Set address alignment for endpoint mode Rick Wertenbroek
2023-04-05 9:23 ` [PATCH v3 00/11] PCI: rockchip: Fix RK3399 PCIe endpoint controller driver Damien Le Moal
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