From: Bartosz Golaszewski <brgl@bgdev.pl>
To: "Kalle Valo" <kvalo@kernel.org>,
"David S . Miller" <davem@davemloft.net>,
"Eric Dumazet" <edumazet@google.com>,
"Jakub Kicinski" <kuba@kernel.org>,
"Paolo Abeni" <pabeni@redhat.com>,
"Rob Herring" <robh+dt@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Bjorn Andersson" <andersson@kernel.org>,
"Konrad Dybcio" <konrad.dybcio@linaro.org>,
"Catalin Marinas" <catalin.marinas@arm.com>,
"Will Deacon" <will@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Heiko Stuebner" <heiko@sntech.de>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Chris Morgan" <macromorgan@hotmail.com>,
"Linus Walleij" <linus.walleij@linaro.org>,
"Geert Uytterhoeven" <geert+renesas@glider.be>,
"Arnd Bergmann" <arnd@arndb.de>,
"Neil Armstrong" <neil.armstrong@linaro.org>,
"Nícolas F . R . A . Prado" <nfraprado@collabora.com>,
"Marek Szyprowski" <m.szyprowski@samsung.com>,
"Peng Fan" <peng.fan@nxp.com>,
"Robert Richter" <rrichter@amd.com>,
"Dan Williams" <dan.j.williams@intel.com>,
"Jonathan Cameron" <Jonathan.Cameron@huawei.com>,
"Terry Bowman" <terry.bowman@amd.com>,
"Kuppuswamy Sathyanarayanan"
<sathyanarayanan.kuppuswamy@linux.intel.com>,
"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
"Huacai Chen" <chenhuacai@kernel.org>,
"Alex Elder" <elder@linaro.org>,
"Srini Kandagatla" <srinivas.kandagatla@linaro.org>,
"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>
Cc: linux-wireless@vger.kernel.org, netdev@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-msm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org,
Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Subject: [RFC 8/9] PCI/pwrseq: add a pwrseq driver for QCA6390
Date: Thu, 4 Jan 2024 14:01:22 +0100 [thread overview]
Message-ID: <20240104130123.37115-9-brgl@bgdev.pl> (raw)
In-Reply-To: <20240104130123.37115-1-brgl@bgdev.pl>
From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Add a PCIe power sequencing driver that's capable of correctly powering
up the ath11k module on QCA6390 using the PCIe pwrseq functionality.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
---
drivers/pci/pcie/pwrseq/Kconfig | 11 +
drivers/pci/pcie/pwrseq/Makefile | 1 +
drivers/pci/pcie/pwrseq/pcie-pwrseq-qca6390.c | 197 ++++++++++++++++++
3 files changed, 209 insertions(+)
create mode 100644 drivers/pci/pcie/pwrseq/pcie-pwrseq-qca6390.c
diff --git a/drivers/pci/pcie/pwrseq/Kconfig b/drivers/pci/pcie/pwrseq/Kconfig
index 010e31f432c9..f9fe555b8506 100644
--- a/drivers/pci/pcie/pwrseq/Kconfig
+++ b/drivers/pci/pcie/pwrseq/Kconfig
@@ -6,3 +6,14 @@ menuconfig PCIE_PWRSEQ
help
Say yes here to enable support for PCIe power sequencing
drivers.
+
+if PCIE_PWRSEQ
+
+config PCIE_PWRSEQ_QCA6390
+ tristate "PCIe Power Sequencing driver for QCA6390"
+ depends on ARCH_QCOM || COMPILE_TEST
+ help
+ Enable support for the PCIe power sequencing driver for the
+ ath11k module of the QCA6390 WLAN/BT chip.
+
+endif
diff --git a/drivers/pci/pcie/pwrseq/Makefile b/drivers/pci/pcie/pwrseq/Makefile
index da99566594f6..da3e02063404 100644
--- a/drivers/pci/pcie/pwrseq/Makefile
+++ b/drivers/pci/pcie/pwrseq/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_PCIE_PWRSEQ) += pwrseq.o
+obj-$(CONFIG_PCIE_PWRSEQ_QCA6390) += pcie-pwrseq-qca6390.o
diff --git a/drivers/pci/pcie/pwrseq/pcie-pwrseq-qca6390.c b/drivers/pci/pcie/pwrseq/pcie-pwrseq-qca6390.c
new file mode 100644
index 000000000000..e9fddbb642fe
--- /dev/null
+++ b/drivers/pci/pcie/pwrseq/pcie-pwrseq-qca6390.c
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2023 Linaro Ltd.
+ */
+
+#include <linux/bitmap.h>
+#include <linux/gpio/consumer.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pcie-pwrseq.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+struct pcie_pwrseq_qca6390_vreg {
+ const char *name;
+ unsigned int load_uA;
+};
+
+struct pcie_pwrseq_qca6390_pdata {
+ struct pcie_pwrseq_qca6390_vreg *vregs;
+ size_t num_vregs;
+ unsigned int delay_msec;
+};
+
+struct pcie_pwrseq_qca6390_ctx {
+ struct pcie_pwrseq pwrseq;
+ const struct pcie_pwrseq_qca6390_pdata *pdata;
+ struct regulator_bulk_data *regs;
+ struct gpio_descs *en_gpios;
+ unsigned long *en_gpios_values;
+};
+
+static struct pcie_pwrseq_qca6390_vreg pcie_pwrseq_qca6390_vregs[] = {
+ {
+ .name = "vddpmu",
+ .load_uA = 1250000,
+ },
+ {
+ .name = "vddpcie1",
+ .load_uA = 35000,
+ },
+ {
+ .name = "vddpcie2",
+ .load_uA = 15000,
+ },
+};
+
+static struct pcie_pwrseq_qca6390_pdata pcie_pwrseq_qca6390_of_data = {
+ .vregs = pcie_pwrseq_qca6390_vregs,
+ .num_vregs = ARRAY_SIZE(pcie_pwrseq_qca6390_vregs),
+ .delay_msec = 16,
+};
+
+static int pcie_pwrseq_qca6390_power_on(struct pcie_pwrseq_qca6390_ctx *ctx)
+{
+ int ret;
+
+ ret = regulator_bulk_enable(ctx->pdata->num_vregs, ctx->regs);
+ if (ret)
+ return ret;
+
+ bitmap_fill(ctx->en_gpios_values, ctx->en_gpios->ndescs);
+
+ ret = gpiod_set_array_value_cansleep(ctx->en_gpios->ndescs,
+ ctx->en_gpios->desc,
+ ctx->en_gpios->info,
+ ctx->en_gpios_values);
+ if (ret) {
+ regulator_bulk_disable(ctx->pdata->num_vregs, ctx->regs);
+ return ret;
+ }
+
+ if (ctx->pdata->delay_msec)
+ msleep(ctx->pdata->delay_msec);
+
+ return 0;
+}
+
+static int pcie_pwrseq_qca6390_power_off(struct pcie_pwrseq_qca6390_ctx *ctx)
+{
+ int ret;
+
+ bitmap_zero(ctx->en_gpios_values, ctx->en_gpios->ndescs);
+
+ ret = gpiod_set_array_value_cansleep(ctx->en_gpios->ndescs,
+ ctx->en_gpios->desc,
+ ctx->en_gpios->info,
+ ctx->en_gpios_values);
+ if (ret)
+ return ret;
+
+ return regulator_bulk_disable(ctx->pdata->num_vregs, ctx->regs);
+}
+
+static void devm_pcie_pwrseq_qca6390_power_off(void *data)
+{
+ struct pcie_pwrseq_qca6390_ctx *ctx = data;
+
+ pcie_pwrseq_qca6390_power_off(ctx);
+}
+
+static int pcie_pwrseq_qca6309_probe(struct platform_device *pdev)
+{
+ struct pcie_pwrseq_qca6390_ctx *ctx;
+ struct device *dev = &pdev->dev;
+ int ret, i;
+
+ ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
+ if (!ctx)
+ return -ENOMEM;
+
+ ctx->pdata = of_device_get_match_data(dev);
+ if (!ctx->pdata)
+ return dev_err_probe(dev, -ENODEV,
+ "Failed to obtain platform data\n");
+
+ if (ctx->pdata->vregs) {
+ ctx->regs = devm_kcalloc(dev, ctx->pdata->num_vregs,
+ sizeof(*ctx->regs), GFP_KERNEL);
+ if (!ctx->regs)
+ return -ENOMEM;
+
+ for (i = 0; i < ctx->pdata->num_vregs; i++)
+ ctx->regs[i].supply = ctx->pdata->vregs[i].name;
+
+ ret = devm_regulator_bulk_get(dev, ctx->pdata->num_vregs,
+ ctx->regs);
+ if (ret < 0)
+ return dev_err_probe(dev, ret,
+ "Failed to get all regulators\n");
+
+ for (i = 0; i < ctx->pdata->num_vregs; i++) {
+ ret = regulator_set_load(ctx->regs[i].consumer,
+ ctx->pdata->vregs[i].load_uA);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to set vreg load\n");
+ }
+ }
+
+ ctx->en_gpios = devm_gpiod_get_array_optional(dev, "enable",
+ GPIOD_OUT_LOW);
+ if (IS_ERR(ctx->en_gpios))
+ return dev_err_probe(dev, PTR_ERR(ctx->en_gpios),
+ "Failed to get enable GPIOs\n");
+
+ ctx->en_gpios_values = devm_bitmap_zalloc(dev, ctx->en_gpios->ndescs,
+ GFP_KERNEL);
+ if (!ctx->en_gpios_values)
+ return -ENOMEM;
+
+ ret = pcie_pwrseq_qca6390_power_on(ctx);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to power on the device\n");
+
+ ret = devm_add_action_or_reset(dev, devm_pcie_pwrseq_qca6390_power_off,
+ ctx);
+ if (ret)
+ return ret;
+
+ ctx->pwrseq.dev = dev;
+
+ ret = devm_pcie_pwrseq_device_enable(dev, &ctx->pwrseq);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to register the pwrseq wrapper\n");
+
+ return 0;
+}
+
+static const struct of_device_id pcie_pwrseq_qca6309_of_match[] = {
+ {
+ .compatible = "pci17cb,1101",
+ .data = &pcie_pwrseq_qca6390_of_data,
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, pcie_pwrseq_qca6309_of_match);
+
+static struct platform_driver pcie_pwrseq_qca6309_driver = {
+ .driver = {
+ .name = "pcie-pwrseq-qca6390",
+ .of_match_table = pcie_pwrseq_qca6309_of_match,
+ },
+ .probe = pcie_pwrseq_qca6309_probe,
+};
+module_platform_driver(pcie_pwrseq_qca6309_driver);
+
+MODULE_AUTHOR("Bartosz Golaszewski <bartosz.golaszewski@linaro.org>");
+MODULE_DESCRIPTION("PCIe Power Sequencing module for QCA6390");
+MODULE_LICENSE("GPL");
--
2.40.1
next prev parent reply other threads:[~2024-01-04 13:02 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-04 13:01 [RFC 0/9] PCI: introduce the concept of power sequencing of PCIe devices Bartosz Golaszewski
2024-01-04 13:01 ` [RFC 1/9] arm64: dts: qcom: sm8250: describe the PCIe port Bartosz Golaszewski
2024-01-04 13:01 ` [RFC 2/9] arm64: dts: qcom: qrb5165-rb5: describe the WLAN module of QCA6390 Bartosz Golaszewski
2024-01-04 13:44 ` Dmitry Baryshkov
2024-01-04 15:13 ` Bartosz Golaszewski
2024-01-04 13:01 ` [RFC 3/9] PCI/portdrv: create platform devices for child OF nodes Bartosz Golaszewski
2024-01-06 1:05 ` Jeff Johnson
2024-01-09 14:43 ` Lukas Wunner
2024-01-10 12:55 ` Bartosz Golaszewski
2024-01-10 13:28 ` Lukas Wunner
2024-01-10 16:26 ` Bartosz Golaszewski
2024-01-10 16:41 ` Lukas Wunner
2024-01-10 20:18 ` Bartosz Golaszewski
2024-01-11 10:42 ` Lukas Wunner
2024-01-11 11:09 ` Bartosz Golaszewski
2024-01-11 15:02 ` Lukas Wunner
2024-01-11 16:16 ` Bartosz Golaszewski
2024-01-11 21:43 ` Geert Uytterhoeven
2024-01-12 9:43 ` Bartosz Golaszewski
2024-01-12 9:47 ` Lukas Wunner
2024-01-12 9:43 ` Lukas Wunner
2024-01-17 23:38 ` Rob Herring
2024-01-10 20:41 ` Dan Williams
2024-01-11 12:40 ` Manivannan Sadhasivam
2024-01-11 15:06 ` Lukas Wunner
2024-01-04 13:01 ` [RFC 4/9] PCI: hold the rescan mutex when scanning for the first time Bartosz Golaszewski
2024-01-04 13:01 ` [RFC 5/9] PCI/pwrseq: add pwrseq core code Bartosz Golaszewski
2024-01-06 1:25 ` Jeff Johnson
2024-01-04 13:01 ` [RFC 6/9] dt-bindings: vendor-prefixes: add a PCI prefix for Qualcomm Atheros Bartosz Golaszewski
2024-01-04 14:33 ` Rob Herring
2024-01-04 14:49 ` Sebastian Reichel
2024-01-08 19:10 ` Rob Herring
2024-01-08 19:22 ` Bartosz Golaszewski
2024-01-09 2:56 ` Rob Herring
2024-01-09 9:17 ` Krzysztof Kozlowski
2024-01-09 9:30 ` Bartosz Golaszewski
2024-01-04 13:01 ` [RFC 7/9] dt-bindings: wireless: ath11k: describe QCA6390 Bartosz Golaszewski
2024-01-04 15:57 ` Krzysztof Kozlowski
2024-01-09 9:13 ` Kalle Valo
2024-01-04 13:01 ` Bartosz Golaszewski [this message]
2024-01-06 1:31 ` [RFC 8/9] PCI/pwrseq: add a pwrseq driver for QCA6390 Jeff Johnson
2024-01-09 9:18 ` Kalle Valo
2024-01-09 9:34 ` Chen-Yu Tsai
2024-01-09 10:09 ` Kalle Valo
2024-01-09 10:14 ` Arnd Bergmann
2024-01-09 10:26 ` Chen-Yu Tsai
2024-01-09 10:38 ` Arnd Bergmann
2024-01-09 16:43 ` Kalle Valo
2024-01-09 16:46 ` Arnd Bergmann
2024-01-04 13:01 ` [RFC 9/9] arm64: defconfig: enable the PCIe power sequencing " Bartosz Golaszewski
2024-01-04 15:11 ` [RFC 0/9] PCI: introduce the concept of power sequencing of PCIe devices Sebastian Reichel
2024-01-08 15:24 ` Neil Armstrong
2024-01-08 16:10 ` Bartosz Golaszewski
2024-01-09 4:08 ` Florian Fainelli
2024-01-09 7:08 ` Chen-Yu Tsai
2024-01-09 7:41 ` Manivannan Sadhasivam
2024-01-09 9:29 ` Geert Uytterhoeven
2024-01-09 9:24 ` Kalle Valo
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