From: Minda Chen <minda.chen@starfivetech.com>
To: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Conor Dooley" <conor@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh+dt@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Daire McNamara" <daire.mcnamara@microchip.com>,
"Emil Renner Berthing" <emil.renner.berthing@canonical.com>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-pci@vger.kernel.org,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Philipp Zabel <p.zabel@pengutronix.de>,
Mason Huo <mason.huo@starfivetech.com>,
Leyfoon Tan <leyfoon.tan@starfivetech.com>,
Kevin Xie <kevin.xie@starfivetech.com>,
Minda Chen <minda.chen@starfivetech.com>
Subject: [PATCH v16 20/22] PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time value
Date: Thu, 28 Mar 2024 17:18:33 +0800 [thread overview]
Message-ID: <20240328091835.14797-21-minda.chen@starfivetech.com> (raw)
In-Reply-To: <20240328091835.14797-1-minda.chen@starfivetech.com>
From: Kevin Xie <kevin.xie@starfivetech.com>
Add the PCIE_RESET_CONFIG_DEVICE_WAIT_MS macro to define the minimum
waiting time between exit from a conventional reset and sending the
first configuration request to the device.
As described in PCI base specification r6.0, section 6.6.1 <Conventional
Reset>, there are two different use cases of the value:
- "With a Downstream Port that does not support Link speeds greater
than 5.0 GT/s, software must wait a minimum of 100 ms following exit
from a Conventional Reset before sending a Configuration Request to
the device immediately below that Port."
- "With a Downstream Port that supports Link speeds greater than
5.0 GT/s, software must wait a minimum of 100 ms after Link training
completes before sending a Configuration Request to the device
immediately below that Port."
Signed-off-by: Kevin Xie <kevin.xie@starfivetech.com>
Reviewed-by: Mason Huo <mason.huo@starfivetech.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/pci.h | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 17fed1846847..6fa59d6aa063 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -22,6 +22,22 @@
*/
#define PCIE_PME_TO_L2_TIMEOUT_US 10000
+/*
+ * As described in PCI base specification r6.0, section 6.6.1 <Conventional
+ * Reset>, there are two different use cases of the value:
+ *
+ * - "With a Downstream Port that does not support Link speeds greater
+ * than 5.0 GT/s, software must wait a minimum of 100 ms following exit
+ * from a Conventional Reset before sending a Configuration Request to
+ * the device immediately below that Port."
+ *
+ * - "With a Downstream Port that supports Link speeds greater than
+ * 5.0 GT/s, software must wait a minimum of 100 ms after Link training
+ * completes before sending a Configuration Request to the device
+ * immediately below that Port."
+ */
+#define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 100
+
extern const unsigned char pcie_link_speed[];
extern bool pci_early_dump;
--
2.17.1
next prev parent reply other threads:[~2024-03-28 9:19 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-28 9:18 [PATCH v16 00/22] Refactoring Microchip PCIe driver and add StarFive PCIe Minda Chen
2024-03-28 9:18 ` [PATCH v16 01/22] dt-bindings: PCI: Add PLDA XpressRICH PCIe host common properties Minda Chen
2024-03-28 9:18 ` [PATCH v16 02/22] PCI: microchip: Move pcie-microchip-host.c to plda directory Minda Chen
2024-03-28 9:18 ` [PATCH v16 03/22] PCI: microchip: Move PLDA IP register macros to pcie-plda.h Minda Chen
2024-03-28 9:18 ` [PATCH v16 04/22] PCI: microchip: Add bridge_addr field to struct mc_pcie Minda Chen
2024-03-28 9:18 ` [PATCH v16 05/22] PCI: microchip: Rename two PCIe data structures Minda Chen
2024-03-28 9:18 ` [PATCH v16 06/22] PCI: microchip: Move PCIe host data structures to plda-pcie.h Minda Chen
2024-03-28 9:18 ` [PATCH v16 07/22] PCI: microchip: Rename two setup functions Minda Chen
2024-03-28 9:18 ` [PATCH v16 08/22] PCI: microchip: Change the argument of plda_pcie_setup_iomems() Minda Chen
2024-03-28 9:18 ` [PATCH v16 09/22] PCI: microchip: Move setup functions to pcie-plda-host.c Minda Chen
2024-03-28 9:18 ` [PATCH v16 10/22] PCI: microchip: Rename interrupt related functions Minda Chen
2024-03-28 9:18 ` [PATCH v16 11/22] PCI: microchip: Add num_events field to struct plda_pcie_rp Minda Chen
2024-03-28 9:18 ` [PATCH v16 12/22] PCI: microchip: Add request_event_irq() callback function Minda Chen
2024-03-28 9:18 ` [PATCH v16 13/22] PCI: microchip: Add INTx and MSI event num to struct plda_event Minda Chen
2024-03-28 9:18 ` [PATCH v16 14/22] PCI: microchip: Add get_events() callback and add PLDA get_event() Minda Chen
2024-03-28 9:18 ` [PATCH v16 15/22] PCI: microchip: Add event irqchip field to host port and add PLDA irqchip Minda Chen
2024-04-30 0:50 ` Minda Chen
2024-04-30 1:10 ` Minda Chen
2024-03-28 9:18 ` [PATCH v16 16/22] PCI: microchip: Move IRQ functions to pcie-plda-host.c Minda Chen
2024-03-28 9:18 ` [PATCH v16 17/22] PCI: plda: Add event bitmap field to struct plda_pcie_rp Minda Chen
2024-03-28 9:18 ` [PATCH v16 18/22] PCI: plda: Add host init/deinit and map bus functions Minda Chen
2024-03-28 9:18 ` [PATCH v16 19/22] dt-bindings: PCI: Add StarFive JH7110 PCIe controller Minda Chen
2024-03-28 9:18 ` Minda Chen [this message]
2024-03-28 9:18 ` [PATCH v16 21/22] PCI: starfive: Add " Minda Chen
2024-03-28 9:18 ` [PATCH v16 22/22] riscv: dts: starfive: add PCIe dts configuration for JH7110 Minda Chen
2024-04-30 0:53 ` 回复: [PATCH v16 00/22] Refactoring Microchip PCIe driver and add StarFive PCIe Minda Chen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240328091835.14797-21-minda.chen@starfivetech.com \
--to=minda.chen@starfivetech.com \
--cc=aou@eecs.berkeley.edu \
--cc=bhelgaas@google.com \
--cc=conor@kernel.org \
--cc=daire.mcnamara@microchip.com \
--cc=devicetree@vger.kernel.org \
--cc=emil.renner.berthing@canonical.com \
--cc=kevin.xie@starfivetech.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=kw@linux.com \
--cc=leyfoon.tan@starfivetech.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=lpieralisi@kernel.org \
--cc=mason.huo@starfivetech.com \
--cc=p.zabel@pengutronix.de \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=robh+dt@kernel.org \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).