From: Sean Anderson <sean.anderson@linux.dev>
To: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
linux-pci@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Thippeswamy Havalige <thippeswamy.havalige@amd.com>,
Michal Simek <michal.simek@amd.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Sean Anderson <sean.anderson@linux.dev>,
stable@vger.kernel.org, Bharat Kumar Gogada <bharatku@xilinx.com>
Subject: [PATCH 2/7] PCI: xilinx-nwl: Fix off-by-one
Date: Mon, 22 Apr 2024 15:58:59 -0400 [thread overview]
Message-ID: <20240422195904.3591683-3-sean.anderson@linux.dev> (raw)
In-Reply-To: <20240422195904.3591683-1-sean.anderson@linux.dev>
IRQs start at 0, so we don't need to subtract 1.
Fixes: 9a181e1093af ("PCI: xilinx-nwl: Modify IRQ chip for legacy interrupts")
Cc: <stable@vger.kernel.org>
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
---
drivers/pci/controller/pcie-xilinx-nwl.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
index 0408f4d612b5..437927e3bcca 100644
--- a/drivers/pci/controller/pcie-xilinx-nwl.c
+++ b/drivers/pci/controller/pcie-xilinx-nwl.c
@@ -371,7 +371,7 @@ static void nwl_mask_intx_irq(struct irq_data *data)
u32 mask;
u32 val;
- mask = 1 << (data->hwirq - 1);
+ mask = 1 << data->hwirq;
raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK);
@@ -385,7 +385,7 @@ static void nwl_unmask_intx_irq(struct irq_data *data)
u32 mask;
u32 val;
- mask = 1 << (data->hwirq - 1);
+ mask = 1 << data->hwirq;
raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK);
--
2.35.1.1320.gc452695387.dirty
next prev parent reply other threads:[~2024-04-22 19:59 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-22 19:58 [PATCH 0/7] PCI: xilinx-nwl: Add phy support Sean Anderson
2024-04-22 19:58 ` [PATCH 1/7] dt-bindings: pci: xilinx-nwl: Add phys Sean Anderson
2024-04-22 21:28 ` Rob Herring
2024-04-22 21:30 ` Sean Anderson
2024-04-23 12:38 ` Rob Herring
2024-04-23 12:44 ` Rob Herring
2024-04-23 15:18 ` Sean Anderson
2024-04-23 18:43 ` kernel test robot
2024-04-22 19:58 ` Sean Anderson [this message]
2024-04-22 19:59 ` [PATCH 3/7] PCI: xilinx-nwl: Fix register misspelling Sean Anderson
2024-04-22 19:59 ` [PATCH 4/7] PCI: xilinx-nwl: Rate-limit misc interrupt messages Sean Anderson
2024-04-22 19:59 ` [PATCH 5/7] PCI: xilinx-nwl: Clean up clock on probe failure/removal Sean Anderson
2024-04-22 19:59 ` [PATCH 6/7] PCI: xilinx-nwl: Add phy support Sean Anderson
2024-04-22 19:59 ` [PATCH 7/7] [RFT] arm64: zynqmp: Add PCIe phys Sean Anderson
2024-04-23 6:15 ` Michal Simek
2024-04-24 9:11 ` Havalige, Thippeswamy
2024-04-24 11:27 ` Michal Simek
2024-04-24 12:37 ` Havalige, Thippeswamy
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