From: Sean Anderson <sean.anderson@linux.dev>
To: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
linux-pci@vger.kernel.org
Cc: Michal Simek <michal.simek@amd.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Thippeswamy Havalige <thippeswamy.havalige@amd.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Sean Anderson <sean.anderson@linux.dev>,
Conor Dooley <conor+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
devicetree@vger.kernel.org
Subject: [PATCH v2 1/7] dt-bindings: pci: xilinx-nwl: Add phys
Date: Mon, 6 May 2024 12:15:04 -0400 [thread overview]
Message-ID: <20240506161510.2841755-2-sean.anderson@linux.dev> (raw)
In-Reply-To: <20240506161510.2841755-1-sean.anderson@linux.dev>
Add phys properties so Linux can power-on/configure the GTR
transcievers.
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
---
Changes in v2:
- Remove phy-names
- Add an example
Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
index 426f90a47f35..693b29039a9b 100644
--- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
@@ -61,6 +61,10 @@ properties:
interrupt-map:
maxItems: 4
+ phys:
+ minItems: 1
+ maxItems: 4
+
power-domains:
maxItems: 1
@@ -110,6 +114,7 @@ examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/xlnx-zynqmp-power.h>
soc {
#address-cells = <2>;
@@ -138,6 +143,7 @@ examples:
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
msi-parent = <&nwl_pcie>;
+ phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>;
power-domains = <&zynqmp_firmware PD_PCIE>;
iommus = <&smmu 0x4d0>;
pcie_intc: legacy-interrupt-controller {
--
2.35.1.1320.gc452695387.dirty
next prev parent reply other threads:[~2024-05-06 16:15 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-06 16:15 [PATCH v2 0/7] PCI: xilinx-nwl: Add phy support Sean Anderson
2024-05-06 16:15 ` Sean Anderson [this message]
2024-05-07 20:06 ` [PATCH v2 1/7] dt-bindings: pci: xilinx-nwl: Add phys Rob Herring
2024-05-07 20:07 ` Sean Anderson
2024-05-06 16:15 ` [PATCH v2 2/7] PCI: xilinx-nwl: Fix off-by-one Sean Anderson
2024-05-08 1:59 ` Bjorn Helgaas
2024-05-09 21:34 ` Sean Anderson
2024-05-06 16:15 ` [PATCH v2 3/7] PCI: xilinx-nwl: Fix register misspelling Sean Anderson
2024-05-06 16:15 ` [PATCH v2 4/7] PCI: xilinx-nwl: Rate-limit misc interrupt messages Sean Anderson
2024-05-06 16:15 ` [PATCH v2 5/7] PCI: xilinx-nwl: Clean up clock on probe failure/removal Sean Anderson
2024-05-06 16:15 ` [PATCH v2 6/7] PCI: xilinx-nwl: Add phy support Sean Anderson
2024-05-06 16:15 ` [PATCH v2 7/7] arm64: zynqmp: Add PCIe phys Sean Anderson
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