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From: Jon Hunter <jonathanh@nvidia.com>
To: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Cc: <thierry.reding@gmail.com>, <bhelgaas@google.com>,
	<robh+dt@kernel.org>, <mark.rutland@arm.com>,
	<lorenzo.pieralisi@arm.com>, <vidyas@nvidia.com>,
	<linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>,
	<devicetree@vger.kernel.org>
Subject: Re: [PATCH V6 26/27] PCI: tegra: Add support for GPIO based PERST#
Date: Thu, 4 Jul 2019 18:23:51 +0100
Message-ID: <2411c2b7-9676-46d6-d4ab-af1ad0b41ce1@nvidia.com> (raw)
In-Reply-To: <84d26bcc-f5d5-6694-98c9-1363d706d76c@nvidia.com>


On 04/07/2019 16:29, Manikanta Maddireddy wrote:
> 
> 
> On 04-Jul-19 8:18 PM, Jon Hunter wrote:
>> On 18/06/2019 19:02, Manikanta Maddireddy wrote:
>>> Tegra PCIe has fixed per port SFIO line to signal PERST#, which can be
>>> controlled by AFI port register. However, if a platform routes a different
>>> GPIO to the PCIe slot, then port register cannot control it. Add support
>>> for GPIO based PERST# signal for such platforms. GPIO number comes from per
>>> port PCIe device tree node. PCIe driver probe doesn't fail if per port
>>> "reset-gpios" property is not populated, make sure that DT property is not
>>> missed for such platforms.
>> Really? So how come on Jetson TK1 I see ...
>>
>> [    1.073165] tegra-pcie 1003000.pcie: failed to get reset GPIO: -2
>>
>>
>> [    1.073210] tegra-pcie: probe of 1003000.pcie failed with error -2
>>
>> And now ethernet is broken? Why has this not been tested on all Tegra
>> platforms? There is no reason why code submitted to upstream by us
>> (people at NVIDIA) have not tested this on our internal test farm. This
>> is disappointing.
> 
> I did verified this patch on our internal TK1 test farm. I also tested
> on TX1 and TX2.
> This issue popped up because below fix in gpiolib driver went in
> at the same time.
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=025bf37725f1929542361eef2245df30badf242e

Ah! OK now that was unlucky. I guess a bisect would have told me that
but it was clear to see PCI was broken and so quicker to debug this
directly. OK, then sorry for the rant!
 
>>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>>> Acked-by: Thierry Reding <treding@nvidia.com>
>>> ---
>>> V6: No change
>>>
>>> V5:
>>> * Updated reset gpio toggle logic to reflect active low usage
>>> * Replaced kasprintf() with devm_kasprintf()
>>> * Updated commit message with more information.
>>>
>>> V4: Using devm_gpiod_get_from_of_node() to get reset-gpios
>>>
>>> V3: Using helper function to get reset-gpios
>>>
>>> V2: Using standard "reset-gpio" property
>>>
>>>  drivers/pci/controller/pci-tegra.c | 45 ++++++++++++++++++++++++++----
>>>  1 file changed, 39 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
>>> index d2841532ff0e..a819bc087a05 100644
>>> --- a/drivers/pci/controller/pci-tegra.c
>>> +++ b/drivers/pci/controller/pci-tegra.c
>>> @@ -17,6 +17,7 @@
>>>  #include <linux/debugfs.h>
>>>  #include <linux/delay.h>
>>>  #include <linux/export.h>
>>> +#include <linux/gpio.h>
>>>  #include <linux/interrupt.h>
>>>  #include <linux/iopoll.h>
>>>  #include <linux/irq.h>
>>> @@ -399,6 +400,8 @@ struct tegra_pcie_port {
>>>  	unsigned int lanes;
>>>  
>>>  	struct phy **phys;
>>> +
>>> +	struct gpio_desc *reset_gpio;
>>>  };
>>>  
>>>  struct tegra_pcie_bus {
>>> @@ -544,15 +547,23 @@ static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
>>>  	unsigned long value;
>>>  
>>>  	/* pulse reset signal */
>>> -	value = afi_readl(port->pcie, ctrl);
>>> -	value &= ~AFI_PEX_CTRL_RST;
>>> -	afi_writel(port->pcie, value, ctrl);
>>> +	if (port->reset_gpio) {
>>> +		gpiod_set_value(port->reset_gpio, 1);
>>> +	} else {
>>> +		value = afi_readl(port->pcie, ctrl);
>>> +		value &= ~AFI_PEX_CTRL_RST;
>>> +		afi_writel(port->pcie, value, ctrl);
>>> +	}
>>>  
>>>  	usleep_range(1000, 2000);
>>>  
>>> -	value = afi_readl(port->pcie, ctrl);
>>> -	value |= AFI_PEX_CTRL_RST;
>>> -	afi_writel(port->pcie, value, ctrl);
>>> +	if (port->reset_gpio) {
>>> +		gpiod_set_value(port->reset_gpio, 0);
>>> +	} else {
>>> +		value = afi_readl(port->pcie, ctrl);
>>> +		value |= AFI_PEX_CTRL_RST;
>>> +		afi_writel(port->pcie, value, ctrl);
>>> +	}
>>>  }
>>>  
>>>  static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
>>> @@ -2199,6 +2210,7 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
>>>  		struct tegra_pcie_port *rp;
>>>  		unsigned int index;
>>>  		u32 value;
>>> +		char *label;
>>>  
>>>  		err = of_pci_get_devfn(port);
>>>  		if (err < 0) {
>>> @@ -2257,6 +2269,27 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
>>>  		if (IS_ERR(rp->base))
>>>  			return PTR_ERR(rp->base);
>>>  
>>> +		label = devm_kasprintf(dev, GFP_KERNEL, "pex-reset-%u", index);
>>> +		if (!label) {
>>> +			dev_err(dev, "failed to create reset GPIO label\n");
>>> +			return -ENOMEM;
>>> +		}
>>> +
>>> +		/*
>>> +		 * Returns null if reset-gpios property is not populated and
>>> +		 * fall back to using AFI per port register to toggle PERST#
>>> +		 * SFIO line.
>>> +		 */
>>> +		rp->reset_gpio = devm_gpiod_get_from_of_node(dev, port,
>>> +							     "reset-gpios", 0,
>>> +							     GPIOD_OUT_LOW,
>>> +							     label);
>>> +		if (IS_ERR(rp->reset_gpio)) {
>>> +			err = PTR_ERR(rp->reset_gpio);
>>> +			dev_err(dev, "failed to get reset GPIO: %d\n", err);
>>> +			return err;
>>> +		}
>>> +
>> So I believe that we can just remove the above. I will give it a test
>> and see.
>>
>> Cheers
>> Jon
>>
> Error check should be modified as follows,
> 
> 	if (PTR_ERR(rp->reset_gpio) == -ENOENT)
> 		rp->reset_gpio = NULL;
> 	else if (IS_ERR(rp->reset_gpio))
>  		return PTR_ERR(rp->reset_gpio);

OK, but I think that this should be ...

+               if (IS_ERR(rp->reset_gpio)) {
+                       if (PTR_ERR(rp->reset_gpio) == -ENOENT) {
+                               rp->reset_gpio = NULL;
+                       } else {
+                               dev_err(dev, "failed to get reset GPIO: %d\n", err);
+                               return PTR_ERR(rp->reset_gpio);
+                       }
+               }
 
Cheers
Jon

-- 
nvpublic

  reply index

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-18 18:01 [PATCH V6 00/27] Enable Tegra PCIe root port features Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 01/27] soc/tegra: pmc: Export tegra_powergate_power_on() Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 02/27] PCI: tegra: Handle failure cases in tegra_pcie_power_on() Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 03/27] PCI: tegra: Rearrange Tegra PCIe driver functions Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 04/27] PCI: tegra: Mask AFI_INTR in runtime suspend Manikanta Maddireddy
2019-06-20 14:27   ` Lorenzo Pieralisi
2019-06-20 14:46     ` Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 05/27] PCI: tegra: Fix PCIe host power up sequence Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 06/27] PCI: tegra: Add PCIe Gen2 link speed support Manikanta Maddireddy
2019-06-20 14:32   ` Lorenzo Pieralisi
2019-06-20 14:57     ` Manikanta Maddireddy
2019-06-20 15:22       ` Lorenzo Pieralisi
2019-06-18 18:01 ` [PATCH V6 07/27] PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 08/27] PCI: tegra: Program UPHY electrical settings for Tegra210 Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 09/27] PCI: tegra: Enable opportunistic UpdateFC and ACK Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 10/27] PCI: tegra: Disable AFI dynamic clock gating Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 11/27] PCI: tegra: Process pending DLL transactions before entering L1 or L2 Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 12/27] PCI: tegra: Enable PCIe xclk clock clamping Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 13/27] PCI: tegra: Increase the deskew retry time Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 14/27] PCI: tegra: Add SW fixup for RAW violations Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 15/27] PCI: tegra: Update flow control timer frequency in Tegra210 Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 16/27] PCI: tegra: Set target speed as Gen1 before starting LTSSM Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 17/27] PCI: tegra: Fix PLLE power down issue due to CLKREQ# signal Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 18/27] PCI: tegra: Program AFI_CACHE* registers only for Tegra20 Manikanta Maddireddy
2019-06-20 16:26   ` Lorenzo Pieralisi
2019-06-20 16:35     ` Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 19/27] PCI: tegra: Change PRSNT_SENSE IRQ log to debug Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 20/27] PCI: tegra: Disable MSI for Tegra PCIe root port Manikanta Maddireddy
2019-06-18 19:48   ` Bjorn Helgaas
2019-06-19  3:55     ` Manikanta Maddireddy
2019-06-19  9:50       ` Lorenzo Pieralisi
2019-06-18 18:02 ` [PATCH V6 21/27] PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of soc struct Manikanta Maddireddy
2019-06-18 18:02 ` [PATCH V6 22/27] dt-bindings: pci: tegra: Document PCIe DPD pinctrl optional prop Manikanta Maddireddy
2019-06-18 18:02 ` [PATCH V6 23/27] arm64: tegra: Add PEX DPD states as pinctrl properties Manikanta Maddireddy
2019-06-20 10:14   ` Thierry Reding
2019-06-18 18:02 ` [PATCH V6 24/27] PCI: tegra: Put PEX CLK & BIAS pads in DPD mode Manikanta Maddireddy
2019-06-18 18:02 ` [PATCH V6 25/27] PCI: Add DT binding for "reset-gpios" property Manikanta Maddireddy
2019-06-18 18:02 ` [PATCH V6 26/27] PCI: tegra: Add support for GPIO based PERST# Manikanta Maddireddy
2019-07-04 14:48   ` Jon Hunter
2019-07-04 15:29     ` Manikanta Maddireddy
2019-07-04 17:23       ` Jon Hunter [this message]
2019-06-18 18:02 ` [PATCH V6 27/27] PCI: tegra: Change link retry log level to debug Manikanta Maddireddy
2019-06-20 10:25 ` [PATCH V6 00/27] Enable Tegra PCIe root port features Thierry Reding
2019-06-20 10:53   ` Lorenzo Pieralisi
2019-06-20 11:14     ` Thierry Reding
2019-06-20 16:46 ` Lorenzo Pieralisi
2019-06-20 17:23   ` Manikanta Maddireddy

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