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[84.72.105.84]) by smtp.gmail.com with ESMTPSA id h7-20020a1709060f4700b006e8d0746969sm4635074ejj.222.2022.04.26.03.46.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Apr 2022 03:46:57 -0700 (PDT) From: Nicolas Frattaroli To: linux-rockchip@lists.infradead.org Cc: linux-rockchip@lists.infradead.org, heiko@sntech.de, Peter Geis , Marc Zyngier , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Peter Geis Subject: Re: [PATCH v8 0/5] Enable rk356x PCIe controller Date: Tue, 26 Apr 2022 12:46:56 +0200 Message-ID: <2599368.pI0oiQkSSZ@archbook> In-Reply-To: <20220423152403.1681222-1-pgwipeout@gmail.com> References: <20220423152403.1681222-1-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Samstag, 23. April 2022 17:23:58 CEST Peter Geis wrote: > This series enables the DesignWare based PCIe controller on the rk356x > series of chips. > We drop the fallback to the core driver due to compatibility issues. > We reset the PCIe controller at driver probe to prevent issues in the > future when firmware / kexec leaves the controller in an unknown state. > We add support for legacy interrupts for cards that lack MSI support > (which is partially broken currently). > We then add the device tree nodes to enable PCIe on the Quartz64 Model > A. Tested-by: Nicolas Frattaroli Tested on a PINE64 Quartz64 Model A. The series was applied to 5.18-rc4, and two devices were tested: Device #1: ASMedia Technology Inc. ASM1142 USB 3.1 Host Controller A USB 3.1 flash drive was plugged into the PCIe USB controller card. Then, the block device was read. Performance was nominal, no errors showed up in dmesg. Device #2: NEC Corporation uPD720200 USB 3.0 Host Controller (rev 03) behind a PLX Technology, Inc. PEX 8608 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba) PCIe switch. (it's a weird card I grabbed off an auction site with both USB and SATA behind a PCIe switch, it's best not to worry about the twisted mind that came up with it.) A USB 3.1 flash drive was plugged into the PCIe controller card's USB 3.0 port. Then, the block device was read. Performance was nominal, no errors appeared in dmesg. 512 megabytes of /dev/urandom were redirected into a file. The file was SHA1 checksummed. The file was then copied onto the mounted USB 3.1 drive which was connected to the PCIe card. The drive was unmounted, then re-mounted, and then a sha1sum of the file on the drive was calculated. The checksums matched. Based on these tests it is my understanding that this patch series is functional for the use cases I have covered. Regards, Nicolas Frattaroli