linux-pci.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: "Sean V Kelley" <sean.v.kelley@linux.intel.com>
To: "Bjorn Helgaas" <helgaas@kernel.org>
Cc: mj@ucw.cz, linux-pci@vger.kernel.org
Subject: Re: [Patch 1/1] lspci: Add available DVSEC details
Date: Thu, 09 Apr 2020 14:13:14 -0700	[thread overview]
Message-ID: <2F6DE20A-485E-4E65-9BF2-59673430366F@linux.intel.com> (raw)
In-Reply-To: <20200409195616.GA62263@google.com>

On 9 Apr 2020, at 12:56, Bjorn Helgaas wrote:

> On Thu, Apr 09, 2020 at 11:32:04AM -0700, Sean V Kelley wrote:
>> Instead of current generic 'unknown' output for DVSEC, add details on
>> Vendor ID, Rev, etc.
>>
>> Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
>> Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com>
>
> Looks good to me.
>
>> +static void
>> +cap_dvsec(struct device *d, int where)
>> +{
>> +  u32 hdr;
>> +
>> +  printf("Designated Vendor Specific Extended Capability:\n");
>

> s/Vendor Specific/Vendor-Specific/ to match the spec usage
> s/ Extended Capability:// to match other lspci capability output (?)
>

Sure, sounds good.

>> +4e:00.0 Unassigned class [ff00]: Intel Corporation Device 0d93
>
>> +        Capabilities: [d00 v1] Vendor Specific Information: ID=0040 
>> Rev=1 Len=04c <?>
>> +        Capabilities: [e00 v1] Designated Vendor Specific Extended 
>> Capability:
>> +                DVSEC Vendor ID=8086 Rev=0 Len=038 <?>
>> +                DVSEC ID=0000 <?>
>> +        Capabilities: [e38 v1] Device Serial Number 
>> 12-34-56-78-90-00-00-00
>> +00: 86 80 93 0d 00 00 10 00 00 00 00 ff 00 00 80 00
>
> Obviously this class code is wrong.  I assume it'll be fixed in real
> hardware, but ironically we've just spent a few days chasing a problem
> because of a Google Edge TPU with invalid class code.  In that case,
> Linux doesn't assign resources to BARs, so things fall apart after
> that.

Wow.  Easy to forget how much depends on it.  Yes, it will be fixed in 
real hardware with real IDs.  :)

Thanks,

Sean


      reply	other threads:[~2020-04-09 21:13 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-09 18:32 [Patch 0/1] pciutils: Add available DVSEC Details Sean V Kelley
2020-04-09 18:32 ` [Patch 1/1] lspci: Add available DVSEC details Sean V Kelley
2020-04-09 19:56   ` Bjorn Helgaas
2020-04-09 21:13     ` Sean V Kelley [this message]

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=2F6DE20A-485E-4E65-9BF2-59673430366F@linux.intel.com \
    --to=sean.v.kelley@linux.intel.com \
    --cc=helgaas@kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=mj@ucw.cz \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).