From: Baruch Siach <baruch@tkos.co.il>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Stanimir Varbanov <svarbanov@mm-sol.com>
Cc: "Baruch Siach" <baruch.siach@siklu.com>,
"Rob Herring" <robh@kernel.org>,
"Kathiravan T" <quic_kathirav@quicinc.com>,
"Selvam Sathappan Periakaruppan" <quic_speriaka@quicinc.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Rob Herring" <robh+dt@kernel.org>,
"Thierry Reding" <thierry.reding@gmail.com>,
"Jonathan Hunter" <jonathanh@nvidia.com>,
"Jingoo Han" <jingoohan1@gmail.com>,
"Gustavo Pimentel" <gustavo.pimentel@synopsys.com>,
"Robert Marko" <robert.marko@sartura.hr>,
"Bryan O'Donoghue" <pure.logic@nexus-software.ie>,
"Pali Rohár" <pali@kernel.org>, "Johan Hovold" <johan@kernel.org>,
linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-tegra@vger.kernel.org
Subject: [PATCH v8 2/3] PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
Date: Tue, 21 Jun 2022 11:54:53 +0300 [thread overview]
Message-ID: <3025d5e1d8da64798db6958f9780c4763fbcac47.1655799816.git.baruch@tkos.co.il> (raw)
In-Reply-To: <cover.1655799816.git.baruch@tkos.co.il>
From: Baruch Siach <baruch.siach@siklu.com>
The PCIE_CAP_LINK1_VAL macro actually defines slot capabilities. Use
PCI_EXP_SLTCAP_* macros to spell its value, and rename it to better
describe its meaning.
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
---
v7:
Use FIELD_PREP for power limit and stale (Pali Rohár)
---
drivers/pci/controller/dwc/pcie-qcom.c | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 2ea13750b492..5ad9be6372f4 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -69,7 +69,20 @@
#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
#define CFG_BRIDGE_SB_INIT BIT(0)
-#define PCIE_CAP_LINK1_VAL 0x2FD7F
+#define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, \
+ 250)
+#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, \
+ 1)
+#define PCIE_CAP_SLOT_VAL (PCI_EXP_SLTCAP_ABP | \
+ PCI_EXP_SLTCAP_PCP | \
+ PCI_EXP_SLTCAP_MRLSP | \
+ PCI_EXP_SLTCAP_AIP | \
+ PCI_EXP_SLTCAP_PIP | \
+ PCI_EXP_SLTCAP_HPS | \
+ PCI_EXP_SLTCAP_HPC | \
+ PCI_EXP_SLTCAP_EIP | \
+ PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
+ PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
#define PCIE20_PARF_Q2A_FLUSH 0x1AC
@@ -1114,7 +1127,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
- writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
+ writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
val &= ~PCI_EXP_LNKCAP_ASPMS;
--
2.35.1
next prev parent reply other threads:[~2022-06-21 8:55 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-21 8:54 [PATCH v8 0/3] PCI: IPQ6018 platform support Baruch Siach
2022-06-21 8:54 ` [PATCH v8 1/3] PCI: dwc: tegra: move GEN3_RELATED DBI register to common header Baruch Siach
2022-06-21 8:54 ` Baruch Siach [this message]
2022-06-21 8:54 ` [PATCH v8 3/3] PCI: qcom: Add IPQ60xx support Baruch Siach
2022-06-21 9:05 ` Johan Hovold
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