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"lorenzo.pieralisi@arm.com" , "jingoohan1@gmail.com" , "gustavo.pimentel@synopsys.com" CC: "mperttunen@nvidia.com" , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-tegra@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "kthota@nvidia.com" , "mmaddireddy@nvidia.com" , "sagar.tv@gmail.com" Subject: RE: [PATCH V3 08/16] PCI: dwc: Add support to enable CDM register check Thread-Topic: [PATCH V3 08/16] PCI: dwc: Add support to enable CDM register check Thread-Index: AQHU9IqfJ6hn1hISv0aqHiMRM1QAkqZAGXpg Date: Wed, 17 Apr 2019 09:39:10 +0000 Message-ID: <305100E33629484CBB767107E4246BBB0A22C0EC@de02wembxa.internal.synopsys.com> References: <20190416192730.15681-1-vidyas@nvidia.com> <20190416192730.15681-9-vidyas@nvidia.com> In-Reply-To: <20190416192730.15681-9-vidyas@nvidia.com> Accept-Language: pt-PT, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-dg-ref: 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Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Tue, Apr 16, 2019 at 20:27:22, Vidya Sagar wrote: > Add support to enable CDM (Configuration Dependent Module) register check > for any data corruption based on the device-tree flag 'enable-cdm-check'. >=20 > Signed-off-by: Vidya Sagar > --- > Changes since [v2]: > * Changed code and commit description to reflect change in flag from > 'cdm-check' to 'enable-cdm-check' >=20 > Changes since [v1]: > * This is a new patch in v2 series >=20 > drivers/pci/controller/dwc/pcie-designware.c | 7 +++++++ > drivers/pci/controller/dwc/pcie-designware.h | 9 +++++++++ > 2 files changed, 16 insertions(+) >=20 > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/c= ontroller/dwc/pcie-designware.c > index 44c0ba078452..5b416f483426 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -503,4 +503,11 @@ void dw_pcie_setup(struct dw_pcie *pci) > break; > } > dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); > + > + if (of_property_read_bool(np, "enable-cdm-check")) { > + val =3D dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); > + val |=3D PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS | > + PCIE_PL_CHK_REG_CHK_REG_START; > + dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); > + } > } > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/c= ontroller/dwc/pcie-designware.h > index fa41d675c48f..7f57fe019fbf 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -83,6 +83,15 @@ > #define PCIE_MISC_CONTROL_1_OFF 0x8BC > #define PCIE_DBI_RO_WR_EN BIT(0) > =20 > +#define PCIE_PL_CHK_REG_CONTROL_STATUS 0xB20 > +#define PCIE_PL_CHK_REG_CHK_REG_START BIT(0) > +#define PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS BIT(1) > +#define PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR BIT(16) > +#define PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR BIT(17) > +#define PCIE_PL_CHK_REG_CHK_REG_COMPLETE BIT(18) > + > +#define PCIE_PL_CHK_REG_ERR_ADDR 0xB28 > + > /* > * iATU Unroll-specific register definitions > * From 4.80 core version the address translation will be made by unroll > --=20 > 2.17.1 Nice. Acked-by: Gustavo Pimentel Thanks, Gustavo