From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0542C10F14 for ; Tue, 23 Apr 2019 09:40:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 684F72077C for ; Tue, 23 Apr 2019 09:40:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=synopsys.com header.i=@synopsys.com header.b="feE6Top6" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726557AbfDWJkp (ORCPT ); Tue, 23 Apr 2019 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vvXzgKBDBVwbYwkDNDl0EUD92OE64nYnjgeAaJBPGgyukyVqoyj/FLEmNjJIZVOblI dBIqNui0TFbWg== Received: from US01WEHTC2.internal.synopsys.com (us01wehtc2.internal.synopsys.com [10.12.239.237]) (using TLSv1.2 with cipher AES128-SHA256 (128/128 bits)) (No client certificate requested) by mailhost.synopsys.com (Postfix) with ESMTPS id ADC11A005D; Tue, 23 Apr 2019 09:40:43 +0000 (UTC) Received: from DE02WEHTCB.internal.synopsys.com (10.225.19.94) by US01WEHTC2.internal.synopsys.com (10.12.239.237) with Microsoft SMTP Server (TLS) id 14.3.408.0; Tue, 23 Apr 2019 02:40:43 -0700 Received: from DE02WEMBXA.internal.synopsys.com ([fe80::a014:7216:77d:d55c]) by DE02WEHTCB.internal.synopsys.com ([::1]) with mapi id 14.03.0415.000; Tue, 23 Apr 2019 11:40:41 +0200 From: Gustavo Pimentel To: Jisheng Zhang , Gustavo Pimentel , Hou Zhiqiang CC: Vidya Sagar , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "thierry.reding@gmail.com" , "jonathanh@nvidia.com" , "kishon@ti.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" , "lorenzo.pieralisi@arm.com" , "jingoohan1@gmail.com" , "devicetree@vger.kernel.org" , "mmaddireddy@nvidia.com" , "kthota@nvidia.com" , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "mperttunen@nvidia.com" , "linux-tegra@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "sagar.tv@gmail.com" Subject: RE: [PATCH V3 04/16] PCI: dwc: Perform dbi regs write lock towards the end Thread-Topic: [PATCH V3 04/16] PCI: dwc: Perform dbi regs write lock towards the end Thread-Index: AQHU9IqKd2QC8WkfMUGD8rhulPpCxqZAHDUQgAeabACAAc8x0A== Date: Tue, 23 Apr 2019 09:40:40 +0000 Message-ID: <305100E33629484CBB767107E4246BBB0A22FA36@de02wembxa.internal.synopsys.com> References: <20190416192730.15681-1-vidyas@nvidia.com> <20190416192730.15681-5-vidyas@nvidia.com> <305100E33629484CBB767107E4246BBB0A22C127@de02wembxa.internal.synopsys.com> <20190422154608.6e6f8ae3@xhacker.debian> In-Reply-To: <20190422154608.6e6f8ae3@xhacker.debian> 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Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Mon, Apr 22, 2019 at 8:54:32, Jisheng Zhang=20 wrote: > On Wed, 17 Apr 2019 09:56:33 +0000 Gustavo Pimentel wrote: >=20 > >=20 > > On Tue, Apr 16, 2019 at 20:27:18, Vidya Sagar wrote= : > >=20 > > > Remove multiple write enable and disable sequences of dbi registers a= s > > > Tegra194 implements writes to BAR-0 register (offset: 0x10) controlle= d by > > > DBI write-lock enable bit thereby not allowing any further writes to = BAR-0 > > > register in config space to take place. Hence disabling write permiss= ion > > > only towards the end. > > > > > > Signed-off-by: Vidya Sagar > > > --- > > > Changes since [v2]: > > > * None > > > > > > Changes since [v1]: > > > * None > > > > > > drivers/pci/controller/dwc/pcie-designware-host.c | 3 --- > > > 1 file changed, 3 deletions(-) > > > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/driv= ers/pci/controller/dwc/pcie-designware-host.c > > > index 2a5332e5ccfa..c0334c92c1a6 100644 > > > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > > > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > > > @@ -683,7 +683,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp) > > > val &=3D 0xffff00ff; > > > val |=3D 0x00000100; > > > dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val); > > > - dw_pcie_dbi_ro_wr_dis(pci); > > > > > > /* Setup bus numbers */ > > > val =3D dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); > > > @@ -723,8 +722,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp) > > > > > > dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); > > > > > > - /* Enable write permission for the DBI read-only register */ > > > - dw_pcie_dbi_ro_wr_en(pci); > > > /* Program correct class for RC */ > > > dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_P= CI); > > > /* Better disable write permission right after the update */ > > > -- > > > 2.17.1 =20 > >=20 > > This setup sequence was written by Jingoo Han, let's check if he did th= is > > by some particular reason. > > Jingoo do you remember why you wrote the code like this? >=20 > FWICT, enabling RO writeable in the setup sequence is introduced in > commit d91dfe5054d4 ("PCI: dwc: Enable write permission for Class Code,=20 > Interrupt Pin updates"). The Reason why not towards the end maybe > only enable the RO writeable when necessary. I also share that belief, in any case, I just want to confirm with the=20 original developer if this was coded like this for some good reason,=20 maybe to force some additional protection. Otherwise, I think the=20 presented patch is harmless. Gustavo >=20 > thanks