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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id t21-20020a170906609500b006e83679d8acsm4700002ejj.185.2022.04.18.08.52.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 18 Apr 2022 08:52:44 -0700 (PDT) Message-ID: <38e60bb2-123b-09cf-d6ef-3a07c6984108@linaro.org> Date: Mon, 18 Apr 2022 17:52:43 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [RFC/RFT 1/6] dt-bindings: phy: rockchip: add pcie3 phy Content-Language: en-US To: Frank Wunderlich , linux-rockchip@lists.infradead.org Cc: Frank Wunderlich , Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Bjorn Helgaas , Philipp Zabel , Johan Jonker , Peter Geis , Michael Riesch , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org References: <20220416135458.104048-1-linux@fw-web.de> <20220416135458.104048-2-linux@fw-web.de> From: Krzysztof Kozlowski In-Reply-To: <20220416135458.104048-2-linux@fw-web.de> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 16/04/2022 15:54, Frank Wunderlich wrote: > From: Frank Wunderlich > > Add a new binding file for Rockchip PCIe V3 phy driver. Thank you for your patch. There is something to discuss/improve. > > Signed-off-by: Frank Wunderlich > --- > .../bindings/phy/rockchip-pcie3-phy.yaml | 77 +++++++++++++++++++ > 1 file changed, 77 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/rockchip-pcie3-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip-pcie3-phy.yaml > new file mode 100644 > index 000000000000..58a8ce175f13 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/rockchip-pcie3-phy.yaml Filename: vendor,hardware so for example "rockchip,pcie3-phy" although Rob proposed recently for other bindings using compatible as a base: https://lore.kernel.org/linux-devicetree/YlhkwvGdcf4ozTzG@robh.at.kernel.org/ > @@ -0,0 +1,77 @@ > +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/rockchip-pcie3-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip PCIe v3 phy > + > +maintainers: > + - Heiko Stuebner > + > +properties: > + compatible: > + enum: > + - rockchip,rk3568-pcie3-phy > + - rockchip,rk3588-pcie3-phy > + > + reg: > + maxItems: 2 > + > + clocks: > + minItems: 1 > + maxItems: 3 > + > + clock-names: > + contains: > + anyOf: > + - enum: [ refclk_m, refclk_n, pclk ] The list should be strictly ordered (defined), so: items: - const: ... - const: ... - const: ... minItems: 1 However the question is - why the clocks have different amount? Is it per different SoC implementation? > + > + "#phy-cells": > + const: 0 > + > + resets: > + maxItems: 1 > + > + reset-names: > + const: phy > + > + rockchip,phy-grf: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: phandle to the syscon managing the phy "general register files" > + > + rockchip,pipe-grf: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: phandle to the syscon managing the pipe "general register files" > + > + rockchip,pcie30-phymode: > + $ref: '/schemas/types.yaml#/definitions/uint32' > + description: | > + use PHY_MODE_PCIE_AGGREGATION if not defined I don't understand the description. Do you mean here a case when the variable is missing? > + minimum: 0x0 > + maximum: 0x4 Please explain these values. Register values should not be part of bindings, but instead some logical behavior of hardware or its logic. > + > + Just one blank line. > +required: > + - compatible > + - reg > + - rockchip,phy-grf phy-cells as well > + > +additionalProperties: false > + > +unevaluatedProperties: false Just one please, additionalProperties. > + > +examples: > + - | > + #include > + pcie30phy: phy@fe8c0000 { > + compatible = "rockchip,rk3568-pcie3-phy"; > + reg = <0x0 0xfe8c0000 0x0 0x20000>; > + #phy-cells = <0>; > + clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>, > + <&cru PCLK_PCIE30PHY>; Align the entry with opening '<'. Usually the most readable is one clock per line. > + clock-names = "refclk_m", "refclk_n", "pclk"; > + resets = <&cru SRST_PCIE30PHY>; > + reset-names = "phy"; > + rockchip,phy-grf = <&pcie30_phy_grf>; > + }; Best regards, Krzysztof