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[2003:ea:8f1f:ad00:e887:ce1a:5d1d:a96e]) by smtp.googlemail.com with ESMTPSA id i59sm36440916wri.3.2021.02.02.12.40.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 02 Feb 2021 12:40:11 -0800 (PST) Subject: [PATCH net-next 3/4] PCI/VPD: Change Chelsio T4 quirk to provide access to full virtual EEPROM address space From: Heiner Kallweit To: Raju Rangoju , Jakub Kicinski , David Miller , Bjorn Helgaas Cc: "linux-pci@vger.kernel.org" , "netdev@vger.kernel.org" References: Message-ID: <3db0112d-8767-fd9a-4e65-ad97a284a866@gmail.com> Date: Tue, 2 Feb 2021 21:38:41 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org cxgb4 uses the full VPD address space for accessing its EEPROM (with some mapping, see t4_eeprom_ptov()). In cudbg_collect_vpd_data() it sets the VPD len to 32K (PCI_VPD_MAX_SIZE), and then back to 2K (CUDBG_VPD_PF_SIZE). Having official (structured) and unofficial (unstructured) VPD data violates the PCI spec, let's set VPD len according to all data that can be accessed via PCI VPD access, no matter of its structure. Signed-off-by: Heiner Kallweit --- drivers/pci/vpd.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/pci/vpd.c b/drivers/pci/vpd.c index db86fe226..90f17f3b7 100644 --- a/drivers/pci/vpd.c +++ b/drivers/pci/vpd.c @@ -630,16 +630,11 @@ static void quirk_chelsio_extend_vpd(struct pci_dev *dev) int func = (dev->device & 0x0f00) >> 8; /* - * If this is a T4 or later based adapter, the special VPD is at offset - * 0x400 for the Physical Functions (the SR-IOV Virtual Functions have - * no VPD Capabilities). The PCI VPD Access core routines will normally - * compute the size of the VPD by parsing the VPD Data Structure at - * offset 0x000. This will result in silent failures when attempting - * to accesses these other VPD areas which are beyond those computed - * limits. + * If this is a T4 or later based adapter, provide access to the full + * virtual EEPROM address space. */ if (chip >= 0x4 && func < 0x8) - pci_set_vpd_size(dev, 2048); + pci_set_vpd_size(dev, PCI_VPD_MAX_SIZE); } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, -- 2.30.0