From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pb0-f46.google.com ([209.85.160.46]:52449 "EHLO mail-pb0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753968Ab2GKO1p (ORCPT ); Wed, 11 Jul 2012 10:27:45 -0400 Message-ID: <4FFD8D58.6060601@gmail.com> Date: Wed, 11 Jul 2012 22:27:36 +0800 From: Jiang Liu MIME-Version: 1.0 To: Taku Izumi CC: Bjorn Helgaas , Don Dutile , Yijing Wang , Yinghai Lu , "Rafael J . Wysocki" , Kenji Kaneshige , Keping Chen , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [RFC PATCH 01/14] PCI: add pcie_flags into struct pci_dev to cache PCIe capabilities register References: <1341935655-5381-1-git-send-email-jiang.liu@huawei.com> <1341935655-5381-2-git-send-email-jiang.liu@huawei.com> <20120711180112.3ae76a2e.izumi.taku@jp.fujitsu.com> In-Reply-To: <20120711180112.3ae76a2e.izumi.taku@jp.fujitsu.com> Content-Type: text/plain; charset=ISO-8859-1 Sender: linux-pci-owner@vger.kernel.org List-ID: On 07/11/2012 05:01 PM, Taku Izumi wrote: >> +++ b/include/linux/pci.h >> @@ -258,6 +258,7 @@ struct pci_dev { >> u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */ >> u8 rom_base_reg; /* which config register controls the ROM */ >> u8 pin; /* which interrupt pin this device uses */ >> + u16 pcie_flags; /* cached PCI-E Capabilities Register */ > > "xxx_flags" sounds like a bit flag. This variable stores a value of PCIe capability > register, doesn't it? How about "pcie_cap_reg" ? Hi Taku, Good suggestion, will change it. Thanks! Gerry