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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id u9-20020a1709061da900b006fe8c831632sm7585849ejh.73.2022.06.21.05.44.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Jun 2022 05:44:15 -0700 (PDT) Message-ID: <4a58c6c4-be0e-e56c-2498-a14ba46b508d@linaro.org> Date: Tue, 21 Jun 2022 14:44:14 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH v3 1/5] dt-bindings: pci: Add ARTPEC-8 PCIe controller Content-Language: en-US To: wangseok.lee@samsung.com, "robh+dt@kernel.org" , "krzk+dt@kernel.org" , "kishon@ti.com" , "vkoul@kernel.org" , "linux-kernel@vger.kernel.org" , "jesper.nilsson@axis.com" , "lars.persson@axis.com" , "bhelgaas@google.com" , "linux-phy@lists.infradead.org" , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "lorenzo.pieralisi@arm.com" , "kw@linux.com" , "linux-arm-kernel@axis.com" , "kernel@axis.com" Cc: Moon-Ki Jun , Sang Min Kim , Dongjin Yang , Yeeun Kim References: <8d806fc9-0067-2c8d-ec41-13787c7644a2@linaro.org> <20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p7> <20220614012713epcms2p810386a5137fbcf6aefc41fe086badc0b@epcms2p8> <20220620075548epcms2p61182d9d7f41fadb1eb139b349bf7486d@epcms2p6> <20220621074244epcms2p23cb631babfb87e5abb416467fb66e521@epcms2p2> From: Krzysztof Kozlowski In-Reply-To: <20220621074244epcms2p23cb631babfb87e5abb416467fb66e521@epcms2p2> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 21/06/2022 09:42, Wangseok Lee wrote: >>>   >>>  samsung,syscon-bus-s-fsys: >>>    description: >>>      Phandle to bus-s path of fsys block, this register >>>      are used for enabling bus-s. >>>    $ref: /schemas/types.yaml#/definitions/phandle >>>   >>>  samsung,syscon-bus-p-fsys: >>>    description: >>>      Phandle to bus-p path of fsys block, this register >>>      are used for enabling bus-p. >>>    $ref: /schemas/types.yaml#/definitions/phandle >> >> This two look unspecific and hacky workaround for missing drivers. Looks >> like instead of implementing interconnect or clock driver, you decided >> to poke some other registers. Why this cannot be an interconnect driver? >> >> > > bus-s, bus-p is a register that exists in the sysreg of the fsys block. > It is the same block as "fsys-sysreg" but is separated separately in > hardware. Two points here: 1. If it is in FSYS, why it cannot be accessed with samsung,fsys-sysreg? 2. If it is only register, shuld be described like this. You must describe item: https://elixir.bootlin.com/linux/v5.18-rc1/source/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml#L42 > So, get resource is performed separately from "fsys-sysreg". > They set pcie slave, dbi related control settings, > naming "bus-x" seems to be interconnect. > I will add this description to property. > I don't think it need to use the interconnect driver, > so please let me know your opinion. Please document both in the bindings and in the driver usage of this register. Writing there "0" or "1" is not enough. If the documentation is good, I am fine with it. If the explanation is obfuscated/not sufficient, it will look like avoiding to implement a driver, which I don't want to accept. Best regards, Krzysztof