From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Subject: Re: [PATCH v2 39/40] iommu/arm-smmu-v3: Add support for PRI To: Bharat Kumar Gogada , "linux-arm-kernel@lists.infradead.org" , "linux-pci@vger.kernel.org" , "linux-acpi@vger.kernel.org" , "devicetree@vger.kernel.org" , "iommu@lists.linux-foundation.org" , "kvm@vger.kernel.org" , "linux-mm@kvack.org" Cc: "joro@8bytes.org" , Will Deacon , Robin Murphy , "alex.williamson@redhat.com" , "tn@semihalf.com" , "liubo95@huawei.com" , "thunder.leizhen@huawei.com" , "xieyisheng1@huawei.com" , "xuzaibo@huawei.com" , "ilias.apalodimas@linaro.org" , "jonathan.cameron@huawei.com" , "liudongdong3@huawei.com" , "shunyong.yang@hxt-semitech.com" , "nwatters@codeaurora.org" , "okaya@codeaurora.org" , "jcrouse@codeaurora.org" , "rfranz@cavium.com" , "dwmw2@infradead.org" , "jacob.jun.pan@linux.intel.com" , "yi.l.liu@intel.com" , "ashok.raj@intel.com" , "kevin.tian@intel.com" , "baolu.lu@linux.intel.com" , "robdclark@gmail.com" , "christian.koenig@amd.com" , Ravikiran Gummaluri References: <20180511190641.23008-1-jean-philippe.brucker@arm.com> <20180511190641.23008-40-jean-philippe.brucker@arm.com> From: Jean-Philippe Brucker Message-ID: <4e36ddb0-f1c3-f434-d330-be2dc9b88bb8@arm.com> Date: Tue, 29 May 2018 11:27:33 +0100 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=windows-1252 Sender: linux-acpi-owner@vger.kernel.org List-ID: On 25/05/18 15:08, Bharat Kumar Gogada wrote: >> + master->can_fault = true; >> + master->ste.prg_resp_needs_ssid = >> pci_prg_resp_requires_prefix(pdev); > > Any reason why this is not cleared in arm_smmu_disable_pri ? Actually, setting it here is wrong. Since we now call enable_pri() lazily, prg_resp_needs_ssid isn't initialized when writing the STE. That bit is read by the SMMU when the PRIQ is full and it needs to auto-respond. Fortunately the PRI doesn't need to be enabled in order to read this bit, so we can move pci_prg_resp_requires_prefix() to add_device() and clear the bit in remove_device(). Thanks for catching this. Jean