Re: [PATCH 1/3] PCI: dwc: Add support for vendor specific capability search

From: Vidya Sagar <vidyas@nvidia.com>
To: Shradha Todi <shradha.t@samsung.com>, <linux-pci@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>
Cc: <jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>,
	<lorenzo.pieralisi@arm.com>, <robh@kernel.org>,
	<bhelgaas@google.com>, <pankaj.dubey@samsung.com>,
	<p.rajanbabu@samsung.com>, <hari.tv@samsung.com>,
	<niyas.ahmed@samsung.com>, <l.mehra@samsung.com>
Subject: Re: [PATCH 1/3] PCI: dwc: Add support for vendor specific capability search
Date: Thu, 27 May 2021 17:24:12 +0530	[thread overview]
Message-ID: <4feba4f0-e6e7-f5ec-6857-6d0779e24318@nvidia.com> (raw)
In-Reply-To: <20210518174618.42089-2-shradha.t@samsung.com>


On 5/18/2021 11:16 PM, Shradha Todi wrote:
> External email: Use caution opening links or attachments
> 
> 
> Add vendor specific extended configuration space capability search API
> using struct dw_pcie pointer for DW controllers.
> 
> Signed-off-by: Shradha Todi <shradha.t@samsung.com>
> ---
>   drivers/pci/controller/dwc/pcie-designware.c | 16 ++++++++++++++++
>   drivers/pci/controller/dwc/pcie-designware.h |  4 ++++
>   2 files changed, 20 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index a945f0c0e73d..348f6f696976 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -90,6 +90,22 @@ static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start,
>          return 0;
>   }
> 
> +u16 dw_pcie_find_vsec_capability(struct dw_pcie *pci, u8 vsec_cap)
> +{
> +       u16 vsec = 0;
> +       u32 header;
> +
> +       while ((vsec = dw_pcie_find_next_ext_capability(pci, vsec,
> +                                       PCI_EXT_CAP_ID_VNDR))) {
> +               header = dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER);
> +               if (PCI_VNDR_HEADER_ID(header) == vsec_cap)
> +                       return vsec;
> +       }
> +
> +       return 0;
> +}
> +EXPORT_SYMBOL_GPL(dw_pcie_find_vsec_capability);
> +
>   u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap)
>   {
>          return dw_pcie_find_next_ext_capability(pci, 0, cap);
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 7d6e9b7576be..307525aaa063 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -155,6 +155,9 @@
>   #define MAX_IATU_IN                    256
>   #define MAX_IATU_OUT                   256
> 
> +/* Synopsys Vendor specific data */
> +#define DW_PCIE_RAS_CAP_ID             0x2
This is not used in this patch. Better to move it to the second patch in 
this series where it is used.

> +
>   struct pcie_port;
>   struct dw_pcie;
>   struct dw_pcie_ep;
> @@ -284,6 +287,7 @@ struct dw_pcie {
> 
>   u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap);
>   u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap);
> +u16 dw_pcie_find_vsec_capability(struct dw_pcie *pci, u8 vsec_cap);
> 
>   int dw_pcie_read(void __iomem *addr, int size, u32 *val);
>   int dw_pcie_write(void __iomem *addr, int size, u32 val);
> --
> 2.17.1
>