From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pz0-f46.google.com ([209.85.210.46]:55283 "EHLO mail-pz0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757742Ab2HUP71 (ORCPT ); Tue, 21 Aug 2012 11:59:27 -0400 Message-ID: <5033B052.7010506@gmail.com> Date: Tue, 21 Aug 2012 23:59:14 +0800 From: Jiang Liu MIME-Version: 1.0 To: Bjorn Helgaas , Hayes Wang CC: Yu Zhao , Dexuan Cui , Don Dutile , Yinghai Lu , Taku Izumi , "Rafael J . Wysocki" , Kenji Kaneshige , Yijing Wang , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH v3 00/32] provide interfaces to access PCIe capabilities registers References: <1343836477-7287-1-git-send-email-jiang.liu@huawei.com> <50325732.3000700@gmail.com> <50325C18.9030207@gmail.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Sender: linux-pci-owner@vger.kernel.org List-ID: Hi Bjorn, Thanks for your help to finalize the patchset. There's another suspicious issue in r8169.c, which directly writes PCI_EXP_DEVCTL_NOSNOOP_EN to PCI_EXP_DEVCTL. I feel it should preserve other bits when setting the NOSNOOP flag. Regards! Gerry diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c index b47d5b3..4104968 100644 --- a/drivers/net/ethernet/realtek/r8169.c +++ b/drivers/net/ethernet/realtek/r8169.c @@ -5405,14 +5384,9 @@ static void rtl_hw_start_8101(struct net_device *dev) tp->event_slow &= ~RxFIFOOver; if (tp->mac_version == RTL_GIGA_MAC_VER_13 || - tp->mac_version == RTL_GIGA_MAC_VER_16) { - int cap = pci_pcie_cap(pdev); - - if (cap) { - pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, - PCI_EXP_DEVCTL_NOSNOOP_EN); - } - } + tp->mac_version == RTL_GIGA_MAC_VER_16) + pcie_capability_write_word(pdev, PCI_EXP_DEVCTL, + PCI_EXP_DEVCTL_NOSNOOP_EN); RTL_W8(Cfg9346, Cfg9346_Unlock);