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* BAR0/1 & enumeration
@ 2012-08-31 19:29 Paolo
  2012-08-31 19:46 ` Matthew Wilcox
  0 siblings, 1 reply; 4+ messages in thread
From: Paolo @ 2012-08-31 19:29 UTC (permalink / raw)
  To: linux-pci

As newbie to the pcie world, I'm seeking help for understanding this:

How does the bios during enumeration finds whether BAR0/1 is set for pointing to
the config-space of its function or to memory space for memory transactions?

Thanks!


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: BAR0/1 & enumeration
  2012-08-31 19:29 BAR0/1 & enumeration Paolo
@ 2012-08-31 19:46 ` Matthew Wilcox
  2012-08-31 19:56   ` Paolo
  0 siblings, 1 reply; 4+ messages in thread
From: Matthew Wilcox @ 2012-08-31 19:46 UTC (permalink / raw)
  To: Paolo; +Cc: linux-pci

On Fri, Aug 31, 2012 at 07:29:50PM +0000, Paolo wrote:
> As newbie to the pcie world, I'm seeking help for understanding this:
> 
> How does the bios during enumeration finds whether BAR0/1 is set for pointing to
> the config-space of its function or to memory space for memory transactions?

BARs point to either memory or I/O space (discriminated by the bottom
bit of the register).  They never point to config space (indeed, since
they are found in config space, that wouldn't make sense).

-- 
Matthew Wilcox				Intel Open Source Technology Centre
"Bill, look, we understand that you're interested in selling us this
operating system, but compare it to ours.  We can't possibly take such
a retrograde step."

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: BAR0/1 & enumeration
  2012-08-31 19:46 ` Matthew Wilcox
@ 2012-08-31 19:56   ` Paolo
  2012-09-01  3:12     ` Jiang Liu
  0 siblings, 1 reply; 4+ messages in thread
From: Paolo @ 2012-08-31 19:56 UTC (permalink / raw)
  To: linux-pci

Not really.

I'm working on a NTB. NTBs are Type-0 headers, like any PCIe end point.
BAR0/1 on NTB can be set as base address for the config-space of its function OR
as based address of the memory space for memory transactions.

Hence my initial question. Looking fwd to some hint.


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: BAR0/1 & enumeration
  2012-08-31 19:56   ` Paolo
@ 2012-09-01  3:12     ` Jiang Liu
  0 siblings, 0 replies; 4+ messages in thread
From: Jiang Liu @ 2012-09-01  3:12 UTC (permalink / raw)
  To: Paolo; +Cc: linux-pci

The genefic PCI/PCIe framework doesn't do any thing special for NTB device,
just treat it as a normal PCI device. The issue you mentioned must be
handled by BIOS/OS driver with device specific knowledge.
--Gerry

On 09/01/2012 03:56 AM, Paolo wrote:
> Not really.
> 
> I'm working on a NTB. NTBs are Type-0 headers, like any PCIe end point.
> BAR0/1 on NTB can be set as base address for the config-space of its function OR
> as based address of the memory space for memory transactions.
> 
> Hence my initial question. Looking fwd to some hint.
> 
> --
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> 


^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2012-09-01  3:12 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-08-31 19:29 BAR0/1 & enumeration Paolo
2012-08-31 19:46 ` Matthew Wilcox
2012-08-31 19:56   ` Paolo
2012-09-01  3:12     ` Jiang Liu

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