From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Jingoo Han <jingoohan1@gmail.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Rob Herring <robh+dt@kernel.org>,
Masahiro Yamada <yamada.masahiro@socionext.com>,
Marc Zyngier <maz@kernel.org>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Masami Hiramatsu <masami.hiramatsu@linaro.org>,
Jassi Brar <jaswinder.singh@linaro.org>
Subject: Re: [PATCH v5 2/6] PCI: uniphier: Add misc interrupt handler to invoke PME and AER
Date: Fri, 7 Aug 2020 19:12:12 +0900 [thread overview]
Message-ID: <50936df1-313c-aa9b-14b5-975f5e4330df@socionext.com> (raw)
In-Reply-To: <293ed6fe-6e73-f664-c26e-0aef744ce933@socionext.com>
On 2020/07/15 19:04, Kunihiko Hayashi wrote:
> Hi Lorenzo,
>
> On 2020/07/14 22:27, Lorenzo Pieralisi wrote:
>> On Thu, Jun 18, 2020 at 05:38:09PM +0900, Kunihiko Hayashi wrote:
>>> The misc interrupts consisting of PME, AER, and Link event, is handled
>>> by INTx handler, however, these interrupts should be also handled by
>>> MSI handler.
>>
>> Define what you mean please.
[snip]
>> I think this is wrong. pp->irq_domain is the DWC MSI domain, how do
>> you know that hwirq 0 *is* the AER/PME interrupt ?
>
> When AER/PME drivers are probed, AER/PME interrupts are registered
> as MSI-0.
>
> The pcie_message_numbers() function refers the following fields of
> PCI registers,
>
> - PCI_EXP_FLAGS_IRQ (for PME)
> - PCI_ERR_ROOT_AER_IRQ (for AER)
>
> and decides AER/PME interrupts numbers in MSI domain.
> Initial values of both fields are 0, so these interrupts are set to MSI-0.
>
> However, pcie_uniphier driver doesn't know that these interrupts are MSI-0.
> Surely using 0 here is wrong.
> I think that the method to get virq for AER/PME from pcieport is needed.
To avoid using hard-coded MSI-0, I'll add new function to get a virq number
corresponding to each service (AER/PME) to portdrv.
I'll update the series in v6.
Thank you,
---
Best Regards
Kunihiko Hayashi
next prev parent reply other threads:[~2020-08-07 10:12 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-18 8:38 [PATCH v5 0/6] PCI: uniphier: Add features for UniPhier PCIe host controller Kunihiko Hayashi
2020-06-18 8:38 ` [PATCH v5 1/6] PCI: dwc: Add msi_host_isr() callback Kunihiko Hayashi
2020-06-18 8:38 ` [PATCH v5 2/6] PCI: uniphier: Add misc interrupt handler to invoke PME and AER Kunihiko Hayashi
2020-06-27 9:48 ` Marc Zyngier
2020-06-29 9:49 ` Kunihiko Hayashi
2020-06-30 13:23 ` Marc Zyngier
2020-07-01 2:18 ` Kunihiko Hayashi
2020-07-10 16:14 ` Lorenzo Pieralisi
2020-07-14 9:27 ` Kunihiko Hayashi
2020-07-14 13:27 ` Lorenzo Pieralisi
2020-07-15 10:04 ` Kunihiko Hayashi
2020-08-07 10:12 ` Kunihiko Hayashi [this message]
2020-06-18 8:38 ` [PATCH v5 3/6] dt-bindings: PCI: uniphier: Add iATU register description Kunihiko Hayashi
2020-06-18 8:38 ` [PATCH v5 4/6] PCI: uniphier: Add iATU register support Kunihiko Hayashi
2020-06-18 8:38 ` [PATCH v5 5/6] PCI: uniphier: Add error message when failed to get phy Kunihiko Hayashi
2020-06-18 8:38 ` [PATCH v5 6/6] PCI: uniphier: Use devm_platform_ioremap_resource_byname() Kunihiko Hayashi
2020-07-10 0:54 ` Kunihiko Hayashi
2020-07-10 13:29 ` Lorenzo Pieralisi
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