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From: Jay Fang <f.fangjian@huawei.com>
To: Sean V Kelley <sean.v.kelley@linux.intel.com>, <mj@ucw.cz>,
	<bhelgaas@google.com>
Cc: <linux-pci@vger.kernel.org>, huangdaode <huangdaode@hisilicon.com>
Subject: Re: [PATCH v5 2/2] pciutils: Decode Compute eXpress Link DVSEC
Date: Sat, 18 Apr 2020 16:36:31 +0800	[thread overview]
Message-ID: <54a9a3f3-aa30-aa2f-1660-15c70ea7dc54@huawei.com> (raw)
In-Reply-To: <20200415004751.2103963-3-sean.v.kelley@linux.intel.com>

On 2020/4/15 8:47, Sean V Kelley wrote:

> 
> [1] https://www.computeexpresslink.org/
> 
> Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com>
> ---
>  lib/header.h        |  20 +++

> +
> +static int
> +is_cxl_cap(struct device *d, int where)
> +{
> +  u32 hdr;
> +  u16 w;
> +
> +  if (!config_fetch(d, where + PCI_DVSEC_HEADER1, 8))
> +    return 0;
> +
> +  /* Check for supported Vendor */
> +  hdr = get_conf_long(d, where + PCI_DVSEC_HEADER1);
> +  w = BITS(hdr, 0, 16);
> +  if (w != PCI_VENDOR_ID_INTEL)
I don't think here checking is quite right. Does only Intel support CXL?
Other Vendors should also be considered.

Thanks
> +    return 0;
> +
> +  /* Check for Designated Vendor-Specific ID */
> +  hdr = get_conf_long(d, where + PCI_DVSEC_HEADER2);
> +  w = BITS(hdr, 0, 16);
> +  if (w == PCI_DVSEC_ID)
> +    return 1;
> +
> +  return 0;
> +}
> +
>  static void
>  cap_dvsec(struct device *d, int where)
>  {
> @@ -947,7 +998,10 @@ show_ext_caps(struct device *d, int type)
>  	    printf("Readiness Time Reporting <?>\n");
>  	    break;
>  	  case PCI_EXT_CAP_ID_DVSEC:
> -	    cap_dvsec(d, where);
> +	    if (is_cxl_cap(d, where))
> +	      cap_cxl(d, where);
> +	    else
> +	      cap_dvsec(d, where);
>  	    break;
>  	  case PCI_EXT_CAP_ID_VF_REBAR:
>  	    printf("VF Resizable BAR <?>\n");
> diff --git a/tests/cap-dvsec-cxl b/tests/cap-dvsec-cxl
> new file mode 100644
> index 0000000..e5d2745
> --- /dev/null
> +++ b/tests/cap-dvsec-cxl
> @@ -0,0 +1,340 @@
> +6b:00.0 Unassigned class [ff00]: Intel Corporation Device 0d93
> +        Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-


  reply	other threads:[~2020-04-18  8:35 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-15  0:47 [PATCH v5 0/2] pciutils: Add basic decode support for CXL DVSEC Sean V Kelley
2020-04-15  0:47 ` [PATCH v5 1/2] pciutils: Decode available DVSEC details Sean V Kelley
2020-04-15  0:47 ` [PATCH v5 2/2] pciutils: Decode Compute eXpress Link DVSEC Sean V Kelley
2020-04-18  8:36   ` Jay Fang [this message]
2020-04-20 16:21     ` Sean V Kelley
2020-04-20 17:47       ` Bjorn Helgaas
2020-04-20 17:54         ` Sean V Kelley
2020-04-27  3:22         ` Jay Fang

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