From: Vidya Sagar <vidyas@nvidia.com>
To: Rob Herring <robh@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: <linux-pci@vger.kernel.org>, Andy Gross <agross@kernel.org>,
Binghui Wang <wangbinghui@hisilicon.com>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Dilip Kota <eswara.kota@linux.intel.com>,
Fabio Estevam <festevam@gmail.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Jerome Brunet <jbrunet@baylibre.com>,
Jesper Nilsson <jesper.nilsson@axis.com>,
Jingoo Han <jingoohan1@gmail.com>,
Jonathan Chocron <jonnyc@amazon.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Kevin Hilman <khilman@baylibre.com>,
"Kishon Vijay Abraham I" <kishon@ti.com>,
Krzysztof Kozlowski <krzk@kernel.org>,
Kukjin Kim <kgene@kernel.org>,
Kunihiko Hayashi <hayashi.kunihiko@socionext.com>,
"Lucas Stach" <l.stach@pengutronix.de>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Masahiro Yamada <yamada.masahiro@socionext.com>,
Murali Karicheri <m-karicheri2@ti.com>,
"Neil Armstrong" <narmstrong@baylibre.com>,
NXP Linux Team <linux-imx@nxp.com>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Pratyush Anand <pratyush.anand@gmail.com>,
Richard Zhu <hongxing.zhu@nxp.com>,
Sascha Hauer <s.hauer@pengutronix.de>,
Shawn Guo <shawnguo@kernel.org>, Shawn Guo <shawn.guo@linaro.org>,
Stanimir Varbanov <svarbanov@mm-sol.com>,
"Thierry Reding" <thierry.reding@gmail.com>,
Xiaowei Song <songxiaowei@hisilicon.com>,
Yue Wang <yue.wang@Amlogic.com>, Marc Zyngier <maz@kernel.org>,
<linux-amlogic@lists.infradead.org>, <linux-arm-kernel@axis.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-arm-msm@vger.kernel.org>, <linux-omap@vger.kernel.org>,
<linux-samsung-soc@vger.kernel.org>,
<linux-tegra@vger.kernel.org>
Subject: Re: [PATCH v2 03/40] PCI: dwc: Allow overriding bridge pci_ops
Date: Sun, 8 Aug 2021 20:43:43 +0530 [thread overview]
Message-ID: <68e3adfb-a79d-3b70-87ed-2e5e1bf7fc93@nvidia.com> (raw)
In-Reply-To: <20200821035420.380495-4-robh@kernel.org>
On 8/21/2020 9:23 AM, Rob Herring wrote:
> In preparation to allow drivers to set their own root and child pci_ops
> instead of using the DWC specific config space ops, we need to make
> the pci_host_bridge pointer available and move setting the bridge->ops
> and bridge->child_ops pointer to before the .host_init() hook.
>
> Cc: Jingoo Han <jingoohan1@gmail.com>
> Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
> drivers/pci/controller/dwc/pcie-designware-host.c | 15 ++++++++++-----
> drivers/pci/controller/dwc/pcie-designware.h | 1 +
> 2 files changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 1d98554db009..b626cc7cd43a 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -344,6 +344,8 @@ int dw_pcie_host_init(struct pcie_port *pp)
> if (!bridge)
> return -ENOMEM;
>
> + pp->bridge = bridge;
> +
> /* Get the I/O and memory ranges from DT */
> resource_list_for_each_entry(win, &bridge->windows) {
> switch (resource_type(win->res)) {
> @@ -445,6 +447,10 @@ int dw_pcie_host_init(struct pcie_port *pp)
> }
> }
>
> + /* Set default bus ops */
> + bridge->ops = &dw_pcie_ops;
> + bridge->child_ops = &dw_pcie_ops;
> +
> if (pp->ops->host_init) {
> ret = pp->ops->host_init(pp);
> if (ret)
> @@ -452,7 +458,6 @@ int dw_pcie_host_init(struct pcie_port *pp)
> }
>
> bridge->sysdata = pp;
> - bridge->ops = &dw_pcie_ops;
>
> ret = pci_scan_root_bus_bridge(bridge);
> if (ret)
> @@ -654,11 +659,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
> dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
>
> /*
> - * If the platform provides ->rd_other_conf, it means the platform
> - * uses its own address translation component rather than ATU, so
> - * we should not program the ATU here.
> + * If the platform provides its own child bus config accesses, it means
> + * the platform uses its own address translation component rather than
> + * ATU, so we should not program the ATU here.
It is possible that a platform can have its own translation for
configuration accesses and use DWC's ATU for memory/IO address
translations. IMHO, ATU setup for memory/IO address translations
shouldn't be skipped based on platform's '->rd_other_conf'
implementation. Ex:- A platform can implement configuration space access
through the ECAM mechanism yet choose to use ATU for memory/IO address
translations.
Thanks,
Vidya Sagar
> */
> - if (!pp->ops->rd_other_conf) {
> + if (pp->bridge->child_ops == &dw_pcie_ops && !pp->ops->rd_other_conf) {
> dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
> PCIE_ATU_TYPE_MEM, pp->mem_base,
> pp->mem_bus_addr, pp->mem_size);
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index f911760dcc69..8b8ea5f3e7af 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -200,6 +200,7 @@ struct pcie_port {
> u32 num_vectors;
> u32 irq_mask[MAX_MSI_CTRLS];
> struct pci_bus *root_bus;
> + struct pci_host_bridge *bridge;
> raw_spinlock_t lock;
> DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
> };
>
next prev parent reply other threads:[~2021-08-08 15:14 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-21 3:53 [PATCH v2 00/40] PCI: dwc: Driver clean-ups Rob Herring
2020-08-21 3:53 ` [PATCH v2 01/40] PCI: Allow root and child buses to have different pci_ops Rob Herring
2020-08-21 3:53 ` [PATCH v2 02/40] PCI: dwc: Use DBI accessors instead of own config accessors Rob Herring
2020-08-21 3:53 ` [PATCH v2 03/40] PCI: dwc: Allow overriding bridge pci_ops Rob Herring
2021-08-08 15:13 ` Vidya Sagar [this message]
2021-08-09 14:52 ` Rob Herring
2020-08-21 3:53 ` [PATCH v2 04/40] PCI: dwc: Add a default pci_ops.map_bus for root port Rob Herring
2020-08-21 3:53 ` [PATCH v2 05/40] PCI: dwc: al: Use pci_ops for child config space accessors Rob Herring
2020-08-21 3:53 ` [PATCH v2 06/40] PCI: dwc: keystone: Use pci_ops for " Rob Herring
2020-08-21 3:53 ` [PATCH v2 07/40] PCI: dwc: tegra: Use pci_ops for root " Rob Herring
2020-08-21 3:53 ` [PATCH v2 08/40] PCI: dwc: meson: " Rob Herring
2020-08-21 3:53 ` [PATCH v2 09/40] PCI: dwc: kirin: " Rob Herring
2020-08-21 3:53 ` [PATCH v2 10/40] PCI: dwc: exynos: " Rob Herring
2020-08-21 3:53 ` [PATCH v2 11/40] PCI: dwc: histb: " Rob Herring
2020-08-21 3:53 ` [PATCH v2 12/40] PCI: dwc: Remove dwc specific config accessor ops Rob Herring
2020-08-21 3:53 ` [PATCH v2 13/40] PCI: dwc: Use generic config accessors Rob Herring
2020-08-21 3:53 ` [PATCH v2 14/40] PCI: Also call .add_bus() callback for root bus Rob Herring
2020-08-21 3:53 ` [PATCH v2 15/40] PCI: dwc: keystone: Convert .scan_bus() callback to use add_bus Rob Herring
2020-08-21 3:53 ` [PATCH v2 16/40] PCI: dwc: Convert to use pci_host_probe() Rob Herring
2020-08-21 3:53 ` [PATCH v2 17/40] PCI: dwc: Remove root_bus pointer Rob Herring
2020-08-21 3:53 ` [PATCH v2 18/40] PCI: dwc: Remove storing of PCI resources Rob Herring
2020-08-21 3:53 ` [PATCH v2 19/40] PCI: dwc: Simplify config space handling Rob Herring
2020-08-21 3:54 ` [PATCH v2 20/40] PCI: dwc/keystone: Drop duplicated 'num-viewport' Rob Herring
2020-08-21 3:54 ` [PATCH v2 21/40] PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init() Rob Herring
2020-08-21 3:54 ` [PATCH v2 22/40] PCI: dwc/imx6: Remove duplicate define PCIE_LINK_WIDTH_SPEED_CONTROL Rob Herring
2020-08-21 3:54 ` [PATCH v2 23/40] PCI: dwc: Add a 'num_lanes' field to struct dw_pcie Rob Herring
2020-08-21 3:54 ` [PATCH v2 24/40] PCI: dwc: Ensure FAST_LINK_MODE is cleared Rob Herring
2020-08-21 3:54 ` [PATCH v2 25/40] PCI: dwc/meson: Drop the duplicate number of lanes setup Rob Herring
2020-08-21 3:54 ` [PATCH v2 26/40] PCI: dwc/meson: Drop unnecessary RC config space initialization Rob Herring
2020-08-21 3:54 ` [PATCH v2 27/40] PCI: dwc/meson: Rework PCI config and DW port logic register accesses Rob Herring
2020-08-21 3:54 ` [PATCH v2 28/40] PCI: dwc/imx6: Use common PCI register definitions Rob Herring
2020-08-21 3:54 ` [PATCH v2 29/40] PCI: dwc/qcom: " Rob Herring
2020-08-21 3:54 ` [PATCH v2 30/40] PCI: dwc: Remove hardcoded PCI_CAP_ID_EXP offset Rob Herring
2020-08-21 3:54 ` [PATCH v2 31/40] PCI: dwc/tegra: Use common Designware port logic register definitions Rob Herring
2020-08-21 3:54 ` [PATCH v2 32/40] PCI: dwc: Remove read_dbi2 code Rob Herring
2020-08-21 3:54 ` [PATCH v2 33/40] PCI: dwc: Make ATU accessors private Rob Herring
2020-08-21 3:54 ` [PATCH v2 34/40] PCI: dwc: Centralize link gen setting Rob Herring
2020-08-21 3:54 ` [PATCH v2 35/40] PCI: dwc: Set PORT_LINK_DLL_LINK_EN in common setup code Rob Herring
2020-08-21 3:54 ` [PATCH v2 36/40] PCI: dwc/intel-gw: Drop unnecessary checking of DT 'device_type' property Rob Herring
2020-08-21 3:54 ` [PATCH v2 37/40] PCI: dwc/intel-gw: Move getting PCI_CAP_ID_EXP offset to intel_pcie_link_setup() Rob Herring
2020-08-21 3:54 ` [PATCH v2 38/40] PCI: dwc/intel-gw: Drop unused max_width Rob Herring
2020-08-21 3:54 ` [PATCH v2 39/40] PCI: dwc: Move N_FTS setup to common setup Rob Herring
2021-08-08 15:01 ` Vidya Sagar
2021-08-09 15:02 ` Rob Herring
2020-08-21 3:54 ` [PATCH v2 40/40] PCI: dwc: Use DBI accessors Rob Herring
2020-09-07 9:35 ` [PATCH v2 00/40] PCI: dwc: Driver clean-ups Lorenzo Pieralisi
2020-09-15 9:12 ` Michael Walle
2020-09-15 22:02 ` Rob Herring
2020-09-16 7:54 ` Michael Walle
2020-09-29 5:23 ` Kishon Vijay Abraham I
2020-09-29 14:32 ` Rob Herring
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