Re: One Question About PCIe BUS Config Type with pcie_bus_safe or pcie_bus_perf On NVMe Device

[Sinan Kaya <okaya@codeaurora.org>]

On 1/20/2018 2:20 PM, Sinan Kaya wrote:
>> In this case, the function *could* receive a Memory Write Request with
>> a 1024-byte data payload.  CPUs normally write at most a cacheline,
>> which is probably smaller than 1024 bytes, so these large writes would
>> most likely be peer-to-peer DMA writes.
> Why do you think that CPU is involved in fetching a memory read response
> to a read request?

Never mind. I realized you started talking about Memory Writes after the
completions in the above paragraph now. Another source for memory write could
be an SOC internal DMA memcpy engine as well as a peer-to-peer access.

> 
> If an endpoint tries to read 4k from system memory, this would be typically
> done by SOC internal fabric not by the CPU. How fast a fabric can feed 1k
> to the endpoint depends on the capability of the fabric. Some fabric might
> do better with 1k, others could be better with 256 bytes.


-- 
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.