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From: Alexander Stein <alexander.stein@ew.tq-group.com>
To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	Marek Vasut <marex@denx.de>
Cc: linux-pci@vger.kernel.org, Fabio Estevam <festevam@gmail.com>,
	Lucas Stach <l.stach@pengutronix.de>,
	Richard Zhu <hongxing.zhu@nxp.com>,
	Rob Herring <robh+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	NXP Linux Team <linux-imx@nxp.com>, Marek Vasut <marex@denx.de>
Subject: Re: [PATCH 1/3] dt-bindings: imx6q-pcie: Handle various clock configurations
Date: Thu, 03 Nov 2022 09:25:12 +0100	[thread overview]
Message-ID: <7630472.EvYhyI6sBW@steina-w> (raw)
In-Reply-To: <20221102215729.147335-1-marex@denx.de>

Hi Marek,

Am Mittwoch, 2. November 2022, 22:57:27 CET schrieb Marek Vasut:
> The i.MX SoCs have various clock configurations routed into the PCIe IP,
> the list of clock is below. Document all those configurations in the DT
> binding document.
> 
> All SoCs: pcie, pcie_bus
> 6QDL, 7D: + pcie_phy
> 6SX:      + pcie_phy          pcie_inbound_axi
> 8MQ:      + pcie_phy pcie_aux
> 8MM, 8MP: +          pcie_aux
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: NXP Linux Team <linux-imx@nxp.com>
> To: devicetree@vger.kernel.org
> ---
>  .../bindings/pci/fsl,imx6q-pcie.yaml          | 74 +++++++++++++++++--
>  1 file changed, 69 insertions(+), 5 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index
> 376e739bcad40..1cfea8ca72576 100644
> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> @@ -14,9 +14,6 @@ description: |+
>    This PCIe host controller is based on the Synopsys DesignWare PCIe IP
>    and thus inherits all the common properties defined in snps,dw-pcie.yaml.
> 
> -allOf:
> -  - $ref: /schemas/pci/snps,dw-pcie.yaml#
> -
>  properties:
>    compatible:
>      enum:
> @@ -60,8 +57,8 @@ properties:
>      items:
>        - const: pcie
>        - const: pcie_bus
> -      - const: pcie_phy
> -      - const: pcie_inbound_axi for imx6sx-pcie, pcie_aux for imx8mq-pcie
> +      - enum: [pcie_phy, pcie_aux]
> +      - enum: [pcie_inbound_axi, pcie_aux]
> 
>    num-lanes:
>      const: 1
> @@ -177,6 +174,73 @@ required:
> 
>  unevaluatedProperties: false
> 
> +allOf:
> +  - $ref: /schemas/pci/snps,dw-pcie.yaml#
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - fsl,imx6sx-pcie
> +              - fsl,imx8mq-pcie
> +    then:
> +      properties:
> +        clocks:
> +          maxItems: 4
> +        clock-names:
> +          maxItems: 4
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: fsl,imx6sx-pcie
> +    then:
> +      properties:
> +        clock-names:
> +          items:
> +            - const: pcie
> +            - const: pcie_bus
> +            - const: pcie_phy
> +            - const: pcie_inbound_axi
> +    else:
> +      if:
> +        properties:
> +          compatible:
> +            contains:
> +              const: fsl,imx8mq-pcie
> +      then:
> +        properties:
> +          clock-names:
> +            items:
> +              - const: pcie
> +              - const: pcie_bus
> +              - const: pcie_phy
> +              - const: pcie_aux
> +      else:
> +        if:
> +          properties:
> +            compatible:
> +              contains:
> +                enum:
> +                  - fsl,imx8mm-pcie
> +                  - fsl,imx8mp-pcie
> +        then:
> +          properties:
> +            clock-names:
> +              items:
> +                - const: pcie
> +                - const: pcie_bus
> +                - const: pcie_aux
> +        else:
> +          properties:
> +            clock-names:
> +              items:
> +                - const: pcie
> +                - const: pcie_bus
> +                - const: pcie_phy
> +
>  examples:
>    - |
>      #include <dt-bindings/clock/imx6qdl-clock.h>

Acked-by: Alexander Stein <alexander.stein@ew.tq-group.com>



      parent reply	other threads:[~2022-11-03  8:25 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-02 21:57 [PATCH 1/3] dt-bindings: imx6q-pcie: Handle various clock configurations Marek Vasut
2022-11-02 21:57 ` [PATCH 2/3] dt-bindings: imx6q-pcie: Handle various PD configurations Marek Vasut
2022-11-03  3:24   ` Rob Herring
2022-11-03  8:29   ` Alexander Stein
2022-11-03 12:32     ` Rob Herring
2022-11-03 16:25       ` Marek Vasut
2022-11-04  7:19         ` Alexander Stein
2022-11-04 11:41           ` Marek Vasut
2022-11-02 21:57 ` [PATCH 3/3] dt-bindings: imx6q-pcie: Handle more resets on legacy platforms Marek Vasut
2022-11-03  3:24   ` Rob Herring
2022-11-03  3:24 ` [PATCH 1/3] dt-bindings: imx6q-pcie: Handle various clock configurations Rob Herring
2022-11-03 16:07   ` Marek Vasut
2022-11-03  8:25 ` Alexander Stein [this message]

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