Re: [PATCH V3] PCI: pciehp: Disable ACS Source Validation during hot-remove

From: Vidya Sagar <vidyas@nvidia.com>
To: Lukas Wunner <lukas@wunner.de>
Cc: bhelgaas@google.com, alex.williamson@redhat.com,
	treding@nvidia.com, jonathanh@nvidia.com,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	vsethi@nvidia.com, kthota@nvidia.com, mmaddireddy@nvidia.com,
	sagar.tv@gmail.com
Subject: Re: [PATCH V3] PCI: pciehp: Disable ACS Source Validation during hot-remove
Date: Mon, 31 Jul 2023 01:32:27 +0530	[thread overview]
Message-ID: <7880aa6e-9fc5-c026-138f-42bef3c48b69@nvidia.com> (raw)
In-Reply-To: <20230730194026.GA19962@wunner.de>

Thanks Lukas for the quick review.
I commented inline for the queries/concerns raised.

On 7/31/2023 1:10 AM, Lukas Wunner wrote:
> External email: Use caution opening links or attachments
> 
> 
> On Mon, Jul 31, 2023 at 12:45:19AM +0530, Vidya Sagar wrote:
>> PCIe 6.0, 6.12.1.1 specifies that downstream devices are permitted to
>> send upstream messages before they have been assigned a bus number and
>> such messages have a Requester ID with Bus number set to 00h.
>> If the Downstream port has ACS Source Validation enabled, these messages
>> will be detected as ACS violation error.
>>
>> Hence, disable ACS Source Validation in the bridge device during
>> hot-remove operation and re-enable it after enumeration of the
>> downstream hierarchy but before binding the respective device drivers.
> 
> What are these messages that are sent before assignment of a bus number?
One example is the DRS (Device Readiness Status) message.

> 
> What's the user-visible issue that occurs when they're blocked?
I'm not sure about the issue one can observe when they are blocked, but, 
we have seen one issue when they are not blocked. When an endpoint sends 
a DRS message and an ACS violation is raised for it, the system can 
trigger DPC (Downstream Port Containment) if it is configured to do so 
for ACS violations. Once the DPC is released after handling it, system 
would go for link-up again, which results in root port receiving DRS 
once again from the endpoint and the cycle continues.

> 
> Doesn't disabling Source Validation introduce a security hole because the
> device may spoof messages before Source Validation is re-enabled?
Agree, but this concern is already/has always been  there during boot 
scenario where the link-up happens first and the ACS is enabled at a 
later point and endpoint can spoof messages in between if it wishes so.

> 
> PCIe r6.1 sec 6.12.1.1 does indeed point out that the downstream device
> is *permitted* to send these messages but the Implementation Note
> does *not* prescribe that Source Validation shall be disabled to let them
> through.  It merely points out that the messages may be filtered if
> Source Validation is enabled.
Could you please elaborate on the filtering part. Do you expect this to 
be implemented in the hardware or software?

> 
> Thanks,
> 
> Lukas