From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,NICE_REPLY_A, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85215C64E75 for ; Fri, 27 Nov 2020 09:17:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3C36021D93 for ; Fri, 27 Nov 2020 09:17:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=uni-stuttgart.de header.i=@tik.uni-stuttgart.de header.b="v4s+lJQn" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727802AbgK0JRL (ORCPT ); Fri, 27 Nov 2020 04:17:11 -0500 Received: from mxex2.tik.uni-stuttgart.de ([129.69.192.21]:37614 "EHLO mxex2.tik.uni-stuttgart.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727780AbgK0JRK (ORCPT ); Fri, 27 Nov 2020 04:17:10 -0500 X-Greylist: delayed 156943 seconds by postgrey-1.27 at vger.kernel.org; Fri, 27 Nov 2020 04:17:07 EST Received: from localhost (localhost [127.0.0.1]) by mxex2.tik.uni-stuttgart.de (Postfix) with ESMTP id E5F0D60CB8; Fri, 27 Nov 2020 10:17:05 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=uni-stuttgart.de; h=content-language:content-type:content-type:in-reply-to :mime-version:user-agent:date:date:message-id:subject:subject :references:from:from:received:received; s=dkim; i= @tik.uni-stuttgart.de; t=1606468623; x=1608207424; bh=gh7RsCRxaQ DGscDOCb20KvjkPWfrM38t85OmQRL1Aqc=; b=v4s+lJQnNOMJIRVqPDjyNnT5DM EEi3F5xPN7rB+JyrMgfmLYRBnHZWc2xgdSl4lj7eAXiaBXF7dhCzgluOKA+XLWiw XOdFLGJ55goxrzarVxcUVi0kmX94AAyaEujxKblqXblxjCKa35+fvEAx144vWGrO m5yshf5U3MNxog9SY95W2vDaTV9Xrz8QImcvgHwGwz4k/291oJ8jZyOXa02EFL+h KYy2U126FvhsYx4MpFk733XYAlvWnTS358Zq/oJRHrbpTLLmDenAl51tyqvxgf/r DqKjXKTS3/Z4CmUCpMDTOZ09PK/YUmZ3yXbe8CmTppdQ/TNl5ZVyLU0PyWDw== X-Virus-Scanned: USTUTT mailrelay AV services at mxex2.tik.uni-stuttgart.de Received: from mxex2.tik.uni-stuttgart.de ([127.0.0.1]) by localhost (mxex2.tik.uni-stuttgart.de [127.0.0.1]) (amavisd-new, port 10031) with ESMTP id UQzr3FplSyxf; Fri, 27 Nov 2020 10:17:03 +0100 (CET) Received: from [IPv6:2001:7c0:2050:1:1::6] (unknown [IPv6:2001:7c0:2050:1:1::6]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mxex2.tik.uni-stuttgart.de (Postfix) with ESMTPSA; Fri, 27 Nov 2020 10:17:02 +0100 (CET) From: "=?UTF-8?Q?Stefan_B=c3=bchler?=" To: Thomas Gleixner , sean.v.kelley@linux.intel.com Cc: bhelgaas@google.com, bp@alien8.de, corbet@lwn.net, kar.hin.ong@ni.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, mingo@redhat.com, sassmann@kpanic.de, x86@kernel.org, Greg Kroah-Hartman References: <20200220192930.64820-1-sean.v.kelley@linux.intel.com> <87zh35k5xa.fsf@nanos.tec.linutronix.de> <87blfjk7go.fsf@nanos.tec.linutronix.de> Subject: Re: boot interrupt quirk (also in 4.19.y) breaks serial ports (was: [PATCH v2 0/2] pci: Add boot interrupt quirk mechanism for Xeon chipsets) Message-ID: <7b54abab-fe38-4035-7c23-1f7456359c9e@tik.uni-stuttgart.de> Date: Fri, 27 Nov 2020 10:17:02 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.5.0 MIME-Version: 1.0 In-Reply-To: <87blfjk7go.fsf@nanos.tec.linutronix.de> Content-Type: multipart/mixed; boundary="------------C95D686877BEE3CD8901C903" Content-Language: de-DE Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This is a multi-part message in MIME format. --------------C95D686877BEE3CD8901C903 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Hi tglx, On 11/27/20 12:45 AM, Thomas Gleixner wrote: > Stefan, > > On Wed, Nov 25 2020 at 14:41, Stefan Bühler wrote: >> On 11/25/20 12:54 PM, Thomas Gleixner wrote: >>> On Wed, Sep 16 2020 at 12:12, Stefan Bühler wrote: >>> Can you please provide the output of: >>> >>> for ID in 05:00.0 06:00.0 06:00.1 06:01.0 06:01.1; do lspci -s $ID -vvv; done >> >> 05:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) (prog-if 00 [Normal decode]) >> ... >> Capabilities: > > Can you please run this as root so the Capabilities are accessible? My bad, sorry. I did intend to run it as root, but should have checked the output. Again see attached file. While we're at it: the EEPROM for the PEX8112 is: 00000000 5a 03 3c 00 10 00 00 00 00 00 00 00 b5 10 12 81 |Z.<.............| 00000010 64 00 20 00 00 00 00 01 04 00 01 00 0c 10 00 fe |d. .............| 00000020 fe 03 20 10 f0 10 00 00 00 10 33 00 00 00 70 00 |.. .......3...p.| 00000030 00 00 11 00 48 00 00 00 00 00 34 00 50 00 00 00 |....H.....4.P...| 00000040 04 00 55 66 77 88 |..Ufw.| 00000046 (This is what the firmware tool provided to me writes, although I think the cards usually came pre-flashed with it. They gave me the tool because on some cards the second function on OX16PCI954 was sometimes uninitialized, came up with device id 0x9511 "8-bit bus" (PCI_DEVICE_ID_OXSEMI_16PCI95N) and the kernel tries to treat it as UART too.) I think some time ago I found a PDF to decode this here: https://www.broadcom.com/products/pcie-switches-bridges/pcie-bridges/pex8112#documentation But the broadcom site is completely broken right now (at least for me; there own search for "PEX 8112" links it, but then it says "not found"). Anyway, back then I decoded this to: - `0x5A 0x03`: Magic Header, contains register and shared memory settings - `0x003C` = 60 bytes for configs (10 registers): - `@0x0010`: `0x00000000` -- BAR0: Locate anywhere in 32-bit - `@0x0000`: `0x811210B5` -- Vendor `10B5`, Device `8112` (default) - `@0x0064`: `0x00000020` -- Device Capability: Enable "Support 8-bit Tag" field - `@0x0100`: `0x00010004` -- Power Budget Enhanced Capability Header (default) - `@0x100C`: `0x03FEFE00` -- PCI Control: - PCI-To-PCI Express Retry Count set to 0xFE (default: `0x80`) - PCI Express-to-PCI Retry Count set to 0xFE (default: `0x00`) - `@0x1020`: `0x000010F0` -- GPIO Control - GPIO[1-3] Output enable (GPIO[0] is Output enabled by default) - GPIO Diagnostic Select: `10b` (default: `01b`) - `@0x1000`: `0x00000033` -- Device Initialization (default) - `@0x0070`: `0x00110000` -- Link control: default - `@0x0048`: `0x00000000` -- Device-Specific Control (default 0) - `@0x0034`: `0x00000050` -- PCI Capability pointer `0x50` (default: `0x40`) - Skips (disables) Power Management Capability - Remaining: MSI and PCI Express - `0x0004` bytes for shared memory: - `0x55`, `0x66`, `0x77`, `0x88` TLDR: the most notable part probably being "disabling Power Management Capability" by the EEPROM. cheers, Stefan --------------C95D686877BEE3CD8901C903 Content-Type: text/plain; charset=UTF-8; name="oxford-serial-lspci.txt" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="oxford-serial-lspci.txt" MDU6MDAuMCBQQ0kgYnJpZGdlOiBQTFggVGVjaG5vbG9neSwgSW5jLiBQRVg4MTEyIHgxIExh bmUgUENJIEV4cHJlc3MtdG8tUENJIEJyaWRnZSAocmV2IGFhKSAocHJvZy1pZiAwMCBbTm9y bWFsIGRlY29kZV0pCglQaHlzaWNhbCBTbG90OiAxCglDb250cm9sOiBJL08rIE1lbSsgQnVz TWFzdGVyKyBTcGVjQ3ljbGUtIE1lbVdJTlYtIFZHQVNub29wLSBQYXJFcnItIFN0ZXBwaW5n LSBTRVJSKyBGYXN0QjJCLSBEaXNJTlR4LQoJU3RhdHVzOiBDYXArIDY2TUh6LSBVREYtIEZh c3RCMkItIFBhckVyci0gREVWU0VMPWZhc3QgPlRBYm9ydC0gPFRBYm9ydC0gPE1BYm9ydC0g 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