From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99FD6C433F5 for ; Fri, 30 Sep 2022 12:53:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229743AbiI3MxW (ORCPT ); Fri, 30 Sep 2022 08:53:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229694AbiI3MxV (ORCPT ); Fri, 30 Sep 2022 08:53:21 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03A7A184828 for ; Fri, 30 Sep 2022 05:53:21 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 9C90162320 for ; Fri, 30 Sep 2022 12:53:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EC089C433D6; Fri, 30 Sep 2022 12:53:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1664542400; bh=s0GgRjoQfHC7w1YJLou7xGMxlKW6cCfYRaw2oYBOnkw=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=k/tXuftJHESLvjwqRhFQEvL+CRoDeZri5cnxg6fQqsivj5bwNo3a9aeeCqJ0kCk1z frMj9+l/S5uF24uRW63gfr+nVLvyhuQg1rgh/2kE6KzfJvPaO0bbUQayipQW6jhrUl wCk8TBek9E+JgYCP6ffEs7CGuuu8K17mcoLfC+hMIkF6TmaOW0l7gKHwpJiEIDS2k/ e6+JD6Rq/0SeZsLJ49s20C8vDNAw72oPb2+5/aJ8w3kO3VAeB1aGBZkidoqzB2Gaqr uZ/8rbc2MPs2VvI0nJbs35DtdSLiT1KTTrUeesD1us277wZspwEAaf4EHSmSkeB73y k63ffJVUuT95w== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1oeFW1-00DlqC-OC; Fri, 30 Sep 2022 13:53:17 +0100 Date: Fri, 30 Sep 2022 13:53:14 +0100 Message-ID: <86h70paurp.wl-maz@kernel.org> From: Marc Zyngier To: Kevin Rowland Cc: Bjorn Helgaas , linux-pci@vger.kernel.org, Thomas Gleixner , Manivannan Sadhasivam , Krishna Chaitanya Chundru Subject: Re: ARMv8 SError, panic around msi_set_mask_bit during suspend-to-RAM In-Reply-To: References: <20220928215601.GA1841511@bhelgaas> <86k05m7dkr.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kevin.p.rowland@gmail.com, helgaas@kernel.org, linux-pci@vger.kernel.org, tglx@linutronix.de, manivannan.sadhasivam@linaro.org, quic_krichai@quicinc.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Thu, 29 Sep 2022 21:07:50 +0100, Kevin Rowland wrote: > > On Thu, Sep 29, 2022 at 2:08 AM Marc Zyngier wrote: > > > > On Wed, 28 Sep 2022 17:56:01 -0400, > > Bjorn Helgaas wrote: > > > > > > > At this point I'm wondering why we mask MSIs so late in the suspend > > > > process (right when the last non-boot CPU is taken offline). Shouldn't > > > > we disable/mask these IRQs as part of host controller suspend? > > > > This is what we do for *all* interrupts. The question is really > > whether there is any form of PM involved when accessing the device > > implementing the masking. > I'm afraid I didn't understand this part. What is it that we do for > all interrupts? Mask them when the last CPU in their affinity mask is > taken offline, or mask them as part of the suspend process of the > owning device? Sorry, I wasn't clear at all: *managed* interrupts (which are per-CPU interrupts) are disabled when the corresponding CPU goes down. If you have some extra logic to pull the plug on the RC when the last CPU goes away, it must happen after this disabling phase. Thanks, M. -- Without deviation from the norm, progress is not possible.