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From: Marc Zyngier <maz@kernel.org>
To: Xiaowei Bao <xiaowei.bao@nxp.com>
Cc: Robin Murphy <robin.murphy@arm.com>, Roy Zang <roy.zang@nxp.com>,
	"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"Z.q. Hou" <zhiqiang.hou@nxp.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"M.h. Lian" <minghuan.lian@nxp.com>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"bhelgaas@google.com" <bhelgaas@google.com>,
	"andrew.murray@arm.com" <andrew.murray@arm.com>,
	"frowand.list@gmail.com" <frowand.list@gmail.com>,
	Mingkai Hu <mingkai.hu@nxp.com>
Subject: Re: [PATCH] PCI: layerscape: Add the SRIOV support in host side
Date: Wed, 04 Dec 2019 08:13:53 +0000
Message-ID: <86k17czewu.wl-maz@kernel.org> (raw)
In-Reply-To: <AM5PR04MB3299BFC34A4666B7A9C12B13F55D0@AM5PR04MB3299.eurprd04.prod.outlook.com>

On Wed, 04 Dec 2019 04:34:32 +0000,
Xiaowei Bao <xiaowei.bao@nxp.com> wrote:
> 
> 
> 
> > -----Original Message-----
> > From: Robin Murphy <robin.murphy@arm.com>
> > Sent: 2019年12月3日 23:20
> > To: Marc Zyngier <maz@kernel.org>; Xiaowei Bao <xiaowei.bao@nxp.com>
> > Cc: Roy Zang <roy.zang@nxp.com>; lorenzo.pieralisi@arm.com;
> > devicetree@vger.kernel.org; linux-pci@vger.kernel.org; Z.q. Hou
> > <zhiqiang.hou@nxp.com>; linux-kernel@vger.kernel.org; M.h. Lian
> > <minghuan.lian@nxp.com>; robh+dt@kernel.org;
> > linux-arm-kernel@lists.infradead.org; bhelgaas@google.com;
> > andrew.murray@arm.com; frowand.list@gmail.com; Mingkai Hu
> > <mingkai.hu@nxp.com>
> > Subject: Re: [PATCH] PCI: layerscape: Add the SRIOV support in host side
> > 
> > On 03/12/2019 11:51 am, Marc Zyngier wrote:
> > > On 2019-12-03 01:42, Xiaowei Bao wrote:
> > >>> -----Original Message-----
> > >>> From: Marc Zyngier <maz@misterjones.org>
> > >>> Sent: 2019年12月2日 20:48
> > >>> To: Xiaowei Bao <xiaowei.bao@nxp.com>
> > >>> Cc: robh+dt@kernel.org; frowand.list@gmail.com; M.h. Lian
> > >>> <minghuan.lian@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Roy
> > Zang
> > >>> <roy.zang@nxp.com>; lorenzo.pieralisi@arm.com;
> > >>> andrew.murray@arm.com; bhelgaas@google.com;
> > >>> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> > >>> linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > >>> Z.q. Hou <zhiqiang.hou@nxp.com>
> > >>> Subject: Re: [PATCH] PCI: layerscape: Add the SRIOV support in host
> > >>> side
> > >>>
> > >>> On 2019-12-02 10:45, Xiaowei Bao wrote:
> > >>> > GIC get the map relations of devid and stream id from the msi-map
> > >>> > property of DTS, our platform add this property in u-boot base on
> > >>> > the PCIe device in the bus, but if enable the vf device in kernel,
> > >>> > the vf device msi-map will not set, so the vf device can't work,
> > >>> > this patch purpose is that manage the stream id and device id map
> > >>> > relations dynamically in kernel, and make the new PCIe device work in
> > kernel.
> > >>> >
> > >>> > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> > >>> > ---
> > >>> >  drivers/of/irq.c                            |  9 +++
> > >>> >  drivers/pci/controller/dwc/pci-layerscape.c | 94
> > >>> > +++++++++++++++++++++++++++++
> > >>> >  drivers/pci/probe.c                         |  6 ++
> > >>> >  drivers/pci/remove.c                        |  6 ++
> > >>> >  4 files changed, 115 insertions(+)
> > >>> >
> > >>> > diff --git a/drivers/of/irq.c b/drivers/of/irq.c index
> > >>> > a296eaf..791e609 100644
> > >>> > --- a/drivers/of/irq.c
> > >>> > +++ b/drivers/of/irq.c
> > >>> > @@ -576,6 +576,11 @@ void __init of_irq_init(const struct
> > >>> >of_device_id
> > >>> > *matches)
> > >>> >      }
> > >>> >  }
> > >>> >
> > >>> > +u32 __weak ls_pcie_streamid_fix(struct device *dev, u32 rid) {
> > >>> > +    return rid;
> > >>> > +}
> > >>> > +
> > >>> >  static u32 __of_msi_map_rid(struct device *dev, struct
> > >>> >device_node  **np,
> > >>> >                  u32 rid_in)
> > >>> >  {
> > >>> > @@ -590,6 +595,10 @@ static u32 __of_msi_map_rid(struct device
> > >>> >*dev,  struct device_node **np,
> > >>> >          if (!of_map_rid(parent_dev->of_node, rid_in, "msi-map",
> > >>> >                  "msi-map-mask", np, &rid_out))
> > >>> >              break;
> > >>> > +
> > >>> > +    if (rid_out == rid_in)
> > >>> > +        rid_out = ls_pcie_streamid_fix(parent_dev, rid_in);
> > >>>
> > >>> Over my dead body. Get your firmware to properly program the LUT so
> > >>> that it presents the ITS with a reasonable topology. There is
> > >>> absolutely no way this kind of change makes it into the kernel.
> > >>
> > >> Sorry for this, I know it is not reasonable, but I have no other way,
> > >> as I know, ARM get the mapping of stream ID to request ID from the
> > >> msi-map property of DTS, if add a new device which need the stream ID
> > >> and try to get it from the msi-map of DTS, it will failed and not
> > >> work, yes? So could you give me a better advice to fix this issue, I
> > >> would really appreciate any comments or suggestions, thanks a lot.
> > >
> > > Why can't firmware expose an msi-map/msi-map-mask that has a large
> > > enough range to ensure mapping of VFs? What are the limitations of the
> > > LUT that would prevent this from being configured before the kernel
> > > boots?
> 
> Thanks for your comments, yes, this is the root cause, we only have
> 16 stream IDs for PCIe domain, this is the hardware limitation, if
> there have enough stream IDs, we can expose an msi-map/msi-map-mask
> for all PCIe devices in system, unfortunately, the stream IDs is not
> enough, I think other ARM vendor have same issue that they don't
> have enough stream IDs.

Not that I know off.

I'm using a number of ARM-based, SMMU-equipped HW that works just
fine. SR-IOV is perfectly functional on these platforms, and it seems
that only FSL/NXP HW requires hacks of this sort.

	M.

-- 
Jazz is not dead, it just smells funny.

  reply index

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-02 10:45 Xiaowei Bao
2019-12-02 11:01 ` Lorenzo Pieralisi
2019-12-03  1:27   ` Xiaowei Bao
2019-12-02 12:47 ` Marc Zyngier
2019-12-03  1:42   ` Xiaowei Bao
2019-12-03 11:51     ` Marc Zyngier
2019-12-03 15:20       ` Robin Murphy
2019-12-04  4:34         ` Xiaowei Bao
2019-12-04  8:13           ` Marc Zyngier [this message]
2019-12-04 11:59           ` Robin Murphy
2019-12-05  2:56             ` Xiaowei Bao
2019-12-05 11:11           ` Laurentiu Tudor
2019-12-05 10:44     ` Laurentiu Tudor

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