Re: [PATCH 5/8] PCI: rockchip: Added dtsi entry for PCIe endpoint controller

From: ALOK TIWARI <alok.a.tiwari@oracle.com>
To: Rick Wertenbroek <rick.wertenbroek@gmail.com>,
	alberto.dassatti@heig-vd.ch
Cc: xxm@rock-chips.com, wenrui.li@rock-chips.com,
	rick.wertenbroek@heig-vd.ch, "Rob Herring" <robh+dt@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Heiko Stuebner" <heiko@sntech.de>,
	"Shawn Lin" <shawn.lin@rock-chips.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Jani Nikula" <jani.nikula@intel.com>,
	"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
	"Mikko Kovanen" <mikko.kovanen@aavamobile.com>,
	"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux-pci@vger.kernel.org
Subject: Re: [PATCH 5/8] PCI: rockchip: Added dtsi entry for PCIe endpoint controller
Date: Fri, 27 Jan 2023 14:12:46 +0530	[thread overview]
Message-ID: <871ab2c5-5f11-5ed8-9e2f-500e0cbcdb19@oracle.com> (raw)
In-Reply-To: <20230126135049.708524-6-rick.wertenbroek@gmail.com>

   DTC     arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dtb
../arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi:460.3-52: Warning 
(pci_device_reg): /pcie@f8000000/pcie@0,0:reg: PCI reg address is not 
configuration space
   DTC arch/arm64/boot/dts/amlogic/meson-gxm-s912-libretech-pc.dtb
../arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi:460.3-52: Warning 
(pci_device_reg): /pcie@f8000000/pcie@0,0:reg: PCI reg address is not 
configuration space
   HDRINST usr/include/linux/aio_abi.h
   HDRINST usr/include/linux/am437x-vpfe.h
../arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi:460.3-52: Warning 
(pci_device_reg): /pcie@f8000000/pcie@0,0:reg: PCI reg address is not 
configuration space
   DTC     arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dtb


Thanks,

Alok

On 1/26/2023 7:20 PM, Rick Wertenbroek wrote:
> Added missing PCIe endpoint controller entry in the device tree. This
> entry is documented in :
> Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt
> The status is disabled by default, so it will not be loaded unless
> explicitly chosen to.
>
> Signed-off-by: Rick Wertenbroek <rick.wertenbroek@gmail.com>
> ---
>   arch/arm64/boot/dts/rockchip/rk3399.dtsi | 25 ++++++++++++++++++++++++
>   1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> index 9d5b0e8c9..5f7251118 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -265,6 +265,31 @@ pcie0_intc: interrupt-controller {
>   		};
>   	};
>   
> +	pcie0_ep: pcie-ep@f8000000 {
> +		compatible = "rockchip,rk3399-pcie-ep";
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		rockchip,max-outbound-regions = <32>;
> +		clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
> +			<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
> +		clock-names = "aclk", "aclk-perf",
> +				"hclk", "pm";
> +		max-functions = /bits/ 8 <8>;
> +		num-lanes = <4>;
> +		reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0xfa000000 0x0 0x2000000>;
> +		reg-names = "apb-base", "mem-base";
> +		resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
> +			<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
> +			<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
> +		reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
> +				"pm", "pclk", "aclk";
> +		phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
> +		phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pcie_clkreqnb_cpm>;
> +		status = "disabled";
> +	};
> +
>   	gmac: ethernet@fe300000 {
>   		compatible = "rockchip,rk3399-gmac";
>   		reg = <0x0 0xfe300000 0x0 0x10000>;