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[89.176.112.137]) by smtp.gmail.com with ESMTPSA id oq7sm1924062ejb.63.2020.12.16.10.04.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 16 Dec 2020 10:04:57 -0800 (PST) Subject: Re: [PATCH V4] PCI: rcar: Add L1 link state fix into data abort hook To: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, Bjorn Helgaas , Geert Uytterhoeven , Lorenzo Pieralisi , Wolfram Sang , Yoshihiro Shimoda , linux-renesas-soc@vger.kernel.org References: <20201214203805.GA250639@bjorn-Precision-5520> From: Marek Vasut Message-ID: <87361bf6-0fef-3641-1dcb-21c56a2cf0b0@gmail.com> Date: Wed, 16 Dec 2020 18:56:11 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.5.1 MIME-Version: 1.0 In-Reply-To: <20201214203805.GA250639@bjorn-Precision-5520> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 12/14/20 9:38 PM, Bjorn Helgaas wrote: > On Tue, Dec 08, 2020 at 07:05:09PM +0100, Marek Vasut wrote: >> On 12/8/20 5:40 PM, Bjorn Helgaas wrote: > >>> Does this problem occur in both these cases? >>> >>> 1) When ASPM enters L1, and >>> >>> 2) When software writes PCI_PM_CTRL to put the device in D3hot? >>> >>> IIUC both cases require the link to go to L1. I guess the same >>> software workaround applies to both cases? >> >> Yes > > If ASPM puts the Link in L1 and the device needs to DMA, how does the > Link get back to L0? It cannot, so I would expect the DMA access would fail. > Do we use the same data abort hook? If getting > back to L0 requires help from software, it seems like that would > invalidate the L1 exit latency advertised by the devices. Wouldn't > that mean we couldn't safely enable L1 at all unless the endpoint > could tolerate unlimited exit latency? Possibly, there could be limitations to the L1 support in some corner cases. Does that mean the L1 support should be disabled completely ?