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From: Marc Zyngier <maz@kernel.org>
To: Bharat Kumar Gogada <bharatku@xilinx.com>
Cc: "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Frank Wunderlich <frank-w@public-files.de>,
	Thierry Reding <treding@nvidia.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Rob Herring <robh@kernel.org>, Will Deacon <will@kernel.org>,
	"K. Y. Srinivasan" <kys@microsoft.com>,
	Haiyang Zhang <haiyangz@microsoft.com>,
	Stephen Hemminger <sthemmin@microsoft.com>,
	Michael Kelley <mikelley@microsoft.com>,
	Wei Liu <wei.liu@kernel.org>,
	Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Ryder Lee <ryder.lee@mediatek.com>,
	Marek Vasut <marek.vasut+renesas@gmail.com>,
	Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
	Michal Simek <michals@xilinx.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"linux-hyperv@vger.kernel.org" <linux-hyperv@vger.kernel.org>,
	"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
	"linux-mediatek@lists.infradead.org" 
	<linux-mediatek@lists.infradead.org>,
	"linux-renesas-soc@vger.kernel.org" 
	<linux-renesas-soc@vger.kernel.org>,
	"kernel-team@android.com" <kernel-team@android.com>
Subject: Re: [PATCH v2 05/15] PCI: xilinx: Convert to MSI domains
Date: Wed, 24 Mar 2021 14:45:56 +0000	[thread overview]
Message-ID: <874kh0k3tn.wl-maz@kernel.org> (raw)
In-Reply-To: <BYAPR02MB5559590C1395C15205582976A5639@BYAPR02MB5559.namprd02.prod.outlook.com>

On Wed, 24 Mar 2021 13:56:16 +0000,
Bharat Kumar Gogada <bharatku@xilinx.com> wrote:

> > Thanks for that. Can you please try the following patch and let me know if it
> > helps?
> > 
> > Thanks,
> > 
> > 	M.
> > 
> > diff --git a/drivers/pci/controller/pcie-xilinx.c b/drivers/pci/controller/pcie-
> > xilinx.c
> > index ad9abf405167..14001febf59a 100644
> > --- a/drivers/pci/controller/pcie-xilinx.c
> > +++ b/drivers/pci/controller/pcie-xilinx.c
> > @@ -194,8 +194,18 @@ static struct pci_ops xilinx_pcie_ops = {
> > 
> >  /* MSI functions */
> > 
> > +static void xilinx_msi_top_irq_ack(struct irq_data *d) {
> > +	/*
> > +	 * xilinx_pcie_intr_handler() will have performed the Ack.
> > +	 * Eventually, this should be fixed and the Ack be moved in
> > +	 * the respective callbacks for INTx and MSI.
> > +	 */
> > +}
> > +
> >  static struct irq_chip xilinx_msi_top_chip = {
> >  	.name		= "PCIe MSI",
> > +	.irq_ack	= xilinx_msi_top_irq_ack,
> >  };
> > 
> >  static int xilinx_msi_set_affinity(struct irq_data *d, const struct cpumask
> > *mask, bool force) @@ -206,7 +216,7 @@ static int
> > xilinx_msi_set_affinity(struct irq_data *d, const struct cpumask *mas  static
> > void xilinx_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)  {
> >  	struct xilinx_pcie_port *pcie = irq_data_get_irq_chip_data(data);
> > -	phys_addr_t pa = virt_to_phys(pcie);
> > +	phys_addr_t pa = ALIGN_DOWN(virt_to_phys(pcie), SZ_4K);
> > 
> >  	msg->address_lo = lower_32_bits(pa);
> >  	msg->address_hi = upper_32_bits(pa);
> > @@ -468,7 +478,7 @@ static int xilinx_pcie_init_irq_domain(struct
> > xilinx_pcie_port *port)
> > 
> >  	/* Setup MSI */
> >  	if (IS_ENABLED(CONFIG_PCI_MSI)) {
> > -		phys_addr_t pa = virt_to_phys(port);
> > +		phys_addr_t pa = ALIGN_DOWN(virt_to_phys(port), SZ_4K);
> > 
> >  		ret = xilinx_allocate_msi_domains(port);
> >  		if (ret)
> > 
> Thanks Marc.
> With above patch now everything works fine, tested a Samsung NVMe SSD. 
> tst~# lspci
> 00:00.0 PCI bridge: Xilinx Corporation Device 0706
> 01:00.0 Non-Volatile memory controller: Samsung Electronics Co Ltd NVMe SSD Controller 172Xa/172Xb (rev 01)

Great, thanks for giving it a shot. Can I take this as a Tested-by:
tag?

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

  reply	other threads:[~2021-03-24 14:46 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-22 18:45 [PATCH v2 00/15] PCI/MSI: Getting rid of msi_controller, and other cleanups Marc Zyngier
2021-03-22 18:46 ` [PATCH v2 01/15] PCI: tegra: Convert to MSI domains Marc Zyngier
2021-03-22 18:46 ` [PATCH v2 02/15] PCI: rcar: Don't allocate extra memory for the MSI capture address Marc Zyngier
2021-03-22 18:46 ` [PATCH v2 03/15] PCI: rcar: Convert to MSI domains Marc Zyngier
2021-03-22 18:46 ` [PATCH v2 04/15] PCI: xilinx: Don't allocate extra memory for the MSI capture address Marc Zyngier
2021-03-24 12:35   ` Bharat Kumar Gogada
2021-03-24 12:55     ` Marc Zyngier
2021-03-22 18:46 ` [PATCH v2 05/15] PCI: xilinx: Convert to MSI domains Marc Zyngier
2021-03-24 12:42   ` Bharat Kumar Gogada
2021-03-24 13:15     ` Marc Zyngier
2021-03-24 13:56       ` Bharat Kumar Gogada
2021-03-24 14:45         ` Marc Zyngier [this message]
2021-03-25  4:13           ` Bharat Kumar Gogada
2021-03-22 18:46 ` [PATCH v2 06/15] PCI: hv: Drop msi_controller structure Marc Zyngier
2021-03-22 18:46 ` [PATCH v2 07/15] PCI/MSI: Drop use of msi_controller from core code Marc Zyngier
2021-03-22 18:46 ` [PATCH v2 08/15] PCI/MSI: Kill msi_controller structure Marc Zyngier
2021-03-22 18:46 ` [PATCH v2 09/15] PCI/MSI: Kill default_teardown_msi_irqs() Marc Zyngier
2021-03-22 18:46 ` [PATCH v2 10/15] PCI/MSI: Let PCI host bridges declare their lack of MSI handling Marc Zyngier
2021-03-22 18:46 ` [PATCH v2 11/15] PCI: mediatek: Advertise " Marc Zyngier
2021-03-22 18:46 ` [PATCH v2 12/15] PCI/MSI: Let PCI host bridges declare their reliance on MSI domains Marc Zyngier
2021-03-23 11:45   ` Robin Murphy
2021-03-23 18:09     ` Marc Zyngier
2021-03-23 19:04       ` Robin Murphy
2021-03-24 13:19       ` Lorenzo Pieralisi
2021-03-24 16:11         ` Marc Zyngier
2021-03-22 18:46 ` [PATCH v2 13/15] PCI/MSI: Make pci_host_common_probe() declare its " Marc Zyngier
2021-03-22 18:46 ` [PATCH v2 14/15] PCI/MSI: Document the various ways of ending up with NO_MSI Marc Zyngier
2021-03-22 18:46 ` [PATCH v2 15/15] PCI: Refactor HT advertising of NO_MSI flag Marc Zyngier

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