From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8643DC433DB for ; Wed, 24 Mar 2021 12:56:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 496A161A09 for ; Wed, 24 Mar 2021 12:56:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232800AbhCXMz4 (ORCPT ); Wed, 24 Mar 2021 08:55:56 -0400 Received: from mail.kernel.org ([198.145.29.99]:41828 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233835AbhCXMzo (ORCPT ); Wed, 24 Mar 2021 08:55:44 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 1A9A461A06; Wed, 24 Mar 2021 12:55:44 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1lP32z-003WS0-VE; Wed, 24 Mar 2021 12:55:42 +0000 Date: Wed, 24 Mar 2021 12:55:40 +0000 Message-ID: <878s6ck8xf.wl-maz@kernel.org> From: Marc Zyngier To: Bharat Kumar Gogada Cc: "lorenzo.pieralisi@arm.com" , Bjorn Helgaas , Frank Wunderlich , Thierry Reding , Thomas Gleixner , Rob Herring , Will Deacon , "K. Y. Srinivasan" , Haiyang Zhang , Stephen Hemminger , Michael Kelley , Wei Liu , Thierry Reding , Jonathan Hunter , Ryder Lee , Marek Vasut , Yoshihiro Shimoda , Michal Simek , Paul Walmsley , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-hyperv@vger.kernel.org" , "linux-tegra@vger.kernel.org" , "linux-mediatek@lists.infradead.org" , "linux-renesas-soc@vger.kernel.org" , "kernel-team@android.com" Subject: Re: [PATCH v2 04/15] PCI: xilinx: Don't allocate extra memory for the MSI capture address In-Reply-To: References: <20210322184614.802565-1-maz@kernel.org> <20210322184614.802565-5-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: bharatku@xilinx.com, lorenzo.pieralisi@arm.com, bhelgaas@google.com, frank-w@public-files.de, treding@nvidia.com, tglx@linutronix.de, robh@kernel.org, will@kernel.org, kys@microsoft.com, haiyangz@microsoft.com, sthemmin@microsoft.com, mikelley@microsoft.com, wei.liu@kernel.org, thierry.reding@gmail.com, jonathanh@nvidia.com, ryder.lee@mediatek.com, marek.vasut+renesas@gmail.com, yoshihiro.shimoda.uh@renesas.com, michals@xilinx.com, paul.walmsley@sifive.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-hyperv@vger.kernel.org, linux-tegra@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Wed, 24 Mar 2021 12:35:58 +0000, Bharat Kumar Gogada wrote: > > Thanks Marc for the patch. > > Subject: [PATCH v2 04/15] PCI: xilinx: Don't allocate extra memory for the > > MSI capture address > > > > A long cargo-culted behaviour of PCI drivers is to allocate memory to obtain > > an address that is fed to the controller as the MSI capture address (i.e. the > > MSI doorbell). > > > > But there is no actual requirement for this address to be RAM. > > All it needs to be is a suitable aligned address that will > > *not* be DMA'd to. > > > > Use the physical address of the 'port' data structure as the MSI capture > > address. > > > > Signed-off-by: Marc Zyngier > > --- > > drivers/pci/controller/pcie-xilinx.c | 18 ++++++------------ > > 1 file changed, 6 insertions(+), 12 deletions(-) > > ... > > - msg.address_hi = 0; > > - msg.address_lo = msg_addr; > > + msg.address_hi = upper_32_bits(msg_addr); > > + msg.address_lo = lower_32_bits(msg_addr); > > The XILINX_PCIE_REG_MSIBASE2 register expects 4KB aligned address. > The lower 12-bits are always set to 0 in this register. So we need > to mask the address while programming address to Thanks for the heads up, I'll fix this up. Does it work correctly once the address is aligned? M. -- Without deviation from the norm, progress is not possible.