From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0EE49C433ED for ; Fri, 2 Apr 2021 11:11:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D606261107 for ; Fri, 2 Apr 2021 11:11:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235176AbhDBLLd (ORCPT ); Fri, 2 Apr 2021 07:11:33 -0400 Received: from mail.kernel.org ([198.145.29.99]:60736 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234563AbhDBLLa (ORCPT ); Fri, 2 Apr 2021 07:11:30 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 847C7610A0; Fri, 2 Apr 2021 11:11:27 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1lSHi1-005IZB-HJ; Fri, 02 Apr 2021 12:11:25 +0100 Date: Fri, 02 Apr 2021 12:11:24 +0100 Message-ID: <87blaxeyar.wl-maz@kernel.org> From: Marc Zyngier To: Kishon Vijay Abraham I Cc: Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , , , , , Lokesh Vutla Subject: Re: [PATCH 5/6] PCI: keystone: Add PCI legacy interrupt support for AM654 In-Reply-To: <20210325090026.8843-6-kishon@ti.com> References: <20210325090026.8843-1-kishon@ti.com> <20210325090026.8843-6-kishon@ti.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: kishon@ti.com, bhelgaas@google.com, robh+dt@kernel.org, lorenzo.pieralisi@arm.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, lokeshvutla@ti.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Thu, 25 Mar 2021 09:00:25 +0000, Kishon Vijay Abraham I wrote: > > Add PCI legacy interrupt support for AM654. AM654 has a single HW > interrupt line for all the four legacy interrupts INTA/INTB/INTC/INTD. > The HW interrupt line connected to GIC is a pulse interrupt whereas > the legacy interrupts by definition is level interrupt. In order to > provide level interrupt functionality to edge interrupt line, PCIe > in AM654 has provided IRQ_EOI register. When the SW writes to IRQ_EOI > register after handling the interrupt, the IP checks the state of > legacy interrupt and re-triggers pulse interrupt invoking the handler > again. > > Signed-off-by: Kishon Vijay Abraham I > --- > drivers/pci/controller/dwc/pci-keystone.c | 87 +++++++++++++++++++++-- > 1 file changed, 82 insertions(+), 5 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c > index dfa9a7fcf9b7..84a25207d0d3 100644 > --- a/drivers/pci/controller/dwc/pci-keystone.c > +++ b/drivers/pci/controller/dwc/pci-keystone.c > @@ -118,6 +118,7 @@ struct keystone_pcie { > /* PCI Device ID */ > u32 device_id; > struct device_node *legacy_intc_np; > + struct irq_domain *legacy_irq_domain; > > int msi_host_irq; > int num_lanes; > @@ -289,6 +290,29 @@ static irqreturn_t ks_pcie_handle_error_irq(struct keystone_pcie *ks_pcie) > return IRQ_HANDLED; > } > > +static void ks_pcie_am654_legacy_irq_handler(struct irq_desc *desc) > +{ > + struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); > + struct irq_chip *chip = irq_desc_get_chip(desc); > + int virq, i; > + u32 reg; > + > + chained_irq_enter(chip, desc); > + > + for (i = 0; i < PCI_NUM_INTX; i++) { > + reg = ks_pcie_app_readl(ks_pcie, IRQ_STATUS(i)); > + if (!(reg & INTx_EN)) > + continue; > + > + virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, i); > + generic_handle_irq(virq); I'm on my way to kill irq_linear_revmap(), so I'd rather you didn't add more instances. Consider using irq_find_mapping() instead. > + ks_pcie_app_writel(ks_pcie, IRQ_STATUS(i), INTx_EN); > + ks_pcie_app_writel(ks_pcie, IRQ_EOI, i); What are these writes for? The first one feels like an Ack, and the second one has EOI written over it. If that's what they are, llease move these to a proper irq_chip structure and use the appropriate flow handler, instead of dummy_irq_chip and handle_simple_irq. Thanks, M. -- Without deviation from the norm, progress is not possible.