From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01A76C433FE for ; Tue, 21 Sep 2021 11:01:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DE99760F50 for ; Tue, 21 Sep 2021 11:01:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232288AbhIULDI (ORCPT ); Tue, 21 Sep 2021 07:03:08 -0400 Received: from mail.kernel.org ([198.145.29.99]:38142 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232214AbhIULDI (ORCPT ); Tue, 21 Sep 2021 07:03:08 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id E785960E9C; Tue, 21 Sep 2021 11:01:38 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mSdWq-00C1fJ-Uu; Tue, 21 Sep 2021 12:01:37 +0100 Date: Tue, 21 Sep 2021 12:01:36 +0100 Message-ID: <87ilyuur8v.wl-maz@kernel.org> From: Marc Zyngier To: Mark Kettenis Cc: devicetree@vger.kernel.org, alyssa@rosenzweig.io, Mark Kettenis , Thomas Gleixner , Rob Herring , Hector Martin , Bjorn Helgaas , Florian Fainelli , bcm-kernel-feedback-list@broadcom.com, Nicolas Saenz Julienne , Jim Quinlan , Daire McNamara , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-rpi-kernel@lists.infradead.org Subject: Re: [PATCH v4 0/4] Apple M1 PCIe DT bindings In-Reply-To: <20210827171534.62380-1-mark.kettenis@xs4all.nl> References: <20210827171534.62380-1-mark.kettenis@xs4all.nl> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: mark.kettenis@xs4all.nl, devicetree@vger.kernel.org, alyssa@rosenzweig.io, kettenis@openbsd.org, tglx@linutronix.de, robh+dt@kernel.org, marcan@marcan.st, bhelgaas@google.com, f.fainelli@gmail.com, bcm-kernel-feedback-list@broadcom.com, nsaenz@kernel.org, jim2101024@gmail.com, daire.mcnamara@microchip.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-rpi-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Fri, 27 Aug 2021 18:15:25 +0100, Mark Kettenis wrote: > > From: Mark Kettenis > > This small series adds bindings for the PCIe controller found on the > Apple M1 SoC. > > At this point, the primary consumer for these bindings is U-Boot. > With these bindings U-Boot can bring up the links for the root ports > of the PCIe root complex. A simple OS driver can then provide > standard ECAM access and manage MSI interrupts to provide access > to the built-in Ethernet and XHCI controllers of the Mac mini. > > The Apple controller incorporates Synopsys Designware PCIe logic > to implement its root port. But unlike other hardware currently > supported by U-Boot and the Linux kernel the Apple hardware > integrates multiple root ports. As such the existing bindings > for the DWC PCIe interface can't be used. There is a single ECAM > space for all root space, but separate GPIOs to take the PCI devices > on those ports out of reset. Therefore the standard "reset-gpio" and > "max-link-speed" properties appear on the child nodes representing > the PCI devices that correspond to the individual root ports. > > MSIs are handled by the PCIe controller and translated into "regular > interrupts". A range of 32 MSIs is provided. These 32 MSIs can be > distributed over the root ports as the OS sees fit by programming the > PCIe controller port registers. > > This now adds an MSI controller binding schema and uses the generic > msi-ranges property to specify how the MSIs are mapped to interrupts > on the AIC. I copied some of the description text in the MSI > controller binding schema from msi.txt but it may need some further > tweaks to make sense. > > Patch 2/2 of this series depends on the pinctrl series I sent earlier > and will probably go through Hector Martin's Apple M1 SoC tree. > > > Changelog: > > v4: - Convert MSI controller binding to YAML > - Add generic msi-ranges property to MSI controller binding > - Fix typos/formatting in apple,pcie binding > - Use generic MSI controller binding in apple,pcie > > v3: - Remove unneeded include in example > > v2: - Adjust name for ECAM in "reg-names" > - Drop "phy" registers > - Expand description > - Add description for "interrupts" > - Fix incorrect minItems for "interrupts" > - Fix incorrect MaxItems for "reg-names" > - Document the use of "msi-controller", "msi-parent", "iommu-map" and > "iommu-map-mask" > - Fix "bus-range" and "iommu-map" properties in the example > > Mark Kettenis (4): > dt-bindings: interrupt-controller: Convert MSI controller to > json-schema > dt-bindings: interrupt-controller: msi: Add msi-ranges property > dt-bindings: pci: Add DT bindings for apple,pcie > arm64: apple: Add PCIe node > > .../interrupt-controller/msi-controller.yaml | 42 +++++ > .../devicetree/bindings/pci/apple,pcie.yaml | 165 ++++++++++++++++++ > .../bindings/pci/brcm,stb-pcie.yaml | 1 + > .../bindings/pci/microchip,pcie-host.yaml | 1 + > MAINTAINERS | 1 + > arch/arm64/boot/dts/apple/t8103.dtsi | 63 +++++++ > 6 files changed, 273 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/msi-controller.yaml > create mode 100644 Documentation/devicetree/bindings/pci/apple,pcie.yaml With Rob's comments addressed, and the fix on the M1 RC MMIO region, for the whole series: Acked-by: Marc Zyngier M. -- Without deviation from the norm, progress is not possible.