From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.2 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC16FC433E9 for ; Tue, 9 Mar 2021 11:11:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 980386525D for ; Tue, 9 Mar 2021 11:11:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229656AbhCILKl (ORCPT ); Tue, 9 Mar 2021 06:10:41 -0500 Received: from mail.kernel.org ([198.145.29.99]:47274 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229527AbhCILKk (ORCPT ); Tue, 9 Mar 2021 06:10:40 -0500 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 5098965256; Tue, 9 Mar 2021 11:10:40 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1lJaG6-000WSp-AM; Tue, 09 Mar 2021 11:10:38 +0000 Date: Tue, 09 Mar 2021 11:10:37 +0000 Message-ID: <87r1koy442.wl-maz@kernel.org> From: Marc Zyngier To: Jianjun Wang Cc: Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Ryder Lee , Philipp Zabel , Matthias Brugger , , , , , , Sj Huang , , , , , , , Subject: Re: [v8,4/7] PCI: mediatek-gen3: Add INTx support In-Reply-To: <20210224061132.26526-5-jianjun.wang@mediatek.com> References: <20210224061132.26526-1-jianjun.wang@mediatek.com> <20210224061132.26526-5-jianjun.wang@mediatek.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: jianjun.wang@mediatek.com, bhelgaas@google.com, robh+dt@kernel.org, lorenzo.pieralisi@arm.com, ryder.lee@mediatek.com, p.zabel@pengutronix.de, matthias.bgg@gmail.com, linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, sj.huang@mediatek.com, youlin.pei@mediatek.com, chuanjia.liu@mediatek.com, qizhong.cheng@mediatek.com, sin_jieyang@mediatek.com, drinkcat@chromium.org, Rex-BC.Chen@mediatek.com, anson.chuang@mediatek.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Wed, 24 Feb 2021 06:11:29 +0000, Jianjun Wang wrote: > > Add INTx support for MediaTek Gen3 PCIe controller. > > Signed-off-by: Jianjun Wang > Acked-by: Ryder Lee > --- > drivers/pci/controller/pcie-mediatek-gen3.c | 176 ++++++++++++++++++++ > 1 file changed, 176 insertions(+) > > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c > index c602beb9afec..8b3b5f838b69 100644 > --- a/drivers/pci/controller/pcie-mediatek-gen3.c > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c > @@ -9,6 +9,9 @@ > #include > #include > #include > +#include > +#include > +#include > #include > #include > #include > @@ -45,6 +48,13 @@ > #define PCIE_LINK_STATUS_REG 0x154 > #define PCIE_PORT_LINKUP BIT(8) > > +#define PCIE_INT_ENABLE_REG 0x180 > +#define PCIE_INTX_SHIFT 24 > +#define PCIE_INTX_ENABLE \ > + GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT) > + > +#define PCIE_INT_STATUS_REG 0x184 > + > #define PCIE_TRANS_TABLE_BASE_REG 0x800 > #define PCIE_ATR_SRC_ADDR_MSB_OFFSET 0x4 > #define PCIE_ATR_TRSL_ADDR_LSB_OFFSET 0x8 > @@ -73,6 +83,9 @@ > * @phy: PHY controller block > * @clks: PCIe clocks > * @num_clks: PCIe clocks count for this port > + * @irq: PCIe controller interrupt number > + * @irq_lock: lock protecting IRQ register access > + * @intx_domain: legacy INTx IRQ domain > */ > struct mtk_pcie_port { > struct device *dev; > @@ -83,6 +96,10 @@ struct mtk_pcie_port { > struct phy *phy; > struct clk_bulk_data *clks; > int num_clks; > + > + int irq; > + raw_spinlock_t irq_lock; > + struct irq_domain *intx_domain; > }; > > /** > @@ -199,6 +216,11 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port *port) > val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8); > writel_relaxed(val, port->base + PCIE_PCI_IDS_1); > > + /* Mask all INTx interrupts */ > + val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG); > + val &= ~PCIE_INTX_ENABLE; > + writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG); > + > /* Assert all reset signals */ > val = readl_relaxed(port->base + PCIE_RST_CTRL_REG); > val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB; > @@ -262,6 +284,154 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port *port) > return 0; > } > > +static int mtk_pcie_set_affinity(struct irq_data *data, > + const struct cpumask *mask, bool force) > +{ > + return -EINVAL; > +} > + > +static void mtk_intx_mask(struct irq_data *data) > +{ > + struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); > + unsigned long flags; > + u32 val; > + > + raw_spin_lock_irqsave(&port->irq_lock, flags); > + val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG); > + val &= ~BIT(data->hwirq + PCIE_INTX_SHIFT); > + writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG); > + raw_spin_unlock_irqrestore(&port->irq_lock, flags); > +} > + > +static void mtk_intx_unmask(struct irq_data *data) > +{ > + struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); > + unsigned long flags; > + u32 val; > + > + raw_spin_lock_irqsave(&port->irq_lock, flags); > + val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG); > + val |= BIT(data->hwirq + PCIE_INTX_SHIFT); > + writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG); > + raw_spin_unlock_irqrestore(&port->irq_lock, flags); > +} > + > +/** > + * mtk_intx_eoi > + * @data: pointer to chip specific data > + * > + * As an emulated level IRQ, its interrupt status will remain > + * until the corresponding de-assert message is received; hence that > + * the status can only be cleared when the interrupt has been serviced. > + */ > +static void mtk_intx_eoi(struct irq_data *data) > +{ > + struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); > + unsigned long hwirq; > + > + hwirq = data->hwirq + PCIE_INTX_SHIFT; > + writel_relaxed(BIT(hwirq), port->base + PCIE_INT_STATUS_REG); > +} > + > +static struct irq_chip mtk_intx_irq_chip = { > + .irq_enable = mtk_intx_unmask, > + .irq_disable = mtk_intx_mask, Please get rid of enable/disable. Given that you already have mask/unmask with the *same* implementation, this offers zero benefit. > + .irq_mask = mtk_intx_mask, > + .irq_unmask = mtk_intx_unmask, > + .irq_eoi = mtk_intx_eoi, > + .irq_set_affinity = mtk_pcie_set_affinity, > + .name = "INTx", > +}; [...] Other that that, this look good to me. Thanks, M. -- Without deviation from the norm, progress is not possible.