From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=BAYES_00,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7BFF8C433DB for ; Fri, 26 Mar 2021 10:15:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 38A2A61A49 for ; Fri, 26 Mar 2021 10:15:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229580AbhCZKOk (ORCPT ); Fri, 26 Mar 2021 06:14:40 -0400 Received: from mail.kernel.org ([198.145.29.99]:49630 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229474AbhCZKOc (ORCPT ); Fri, 26 Mar 2021 06:14:32 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 17F4161942; Fri, 26 Mar 2021 10:14:32 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1lPjU5-003xNw-Rc; Fri, 26 Mar 2021 10:14:29 +0000 Date: Fri, 26 Mar 2021 10:14:30 +0000 Message-ID: <87wntufchl.wl-maz@kernel.org> From: Marc Zyngier To: Thomas Gleixner Cc: Megha Dey , linux-kernel@vger.kernel.org, dave.jiang@intel.com, ashok.raj@intel.com, kevin.tian@intel.com, dwmw@amazon.co.uk, x86@kernel.org, tony.luck@intel.com, dan.j.williams@intel.com, jgg@mellanox.com, kvm@vger.kernel.org, iommu@lists.linux-foundation.org, alex.williamson@redhat.com, bhelgaas@google.com, linux-pci@vger.kernel.org, baolu.lu@linux.intel.com, ravi.v.shankar@intel.com Subject: Re: [Patch V2 07/13] irqdomain/msi: Provide msi_alloc/free_store() callbacks In-Reply-To: <87lfabvzrz.fsf@nanos.tec.linutronix.de> References: <1614370277-23235-1-git-send-email-megha.dey@intel.com> <1614370277-23235-8-git-send-email-megha.dey@intel.com> <8735wjrwjm.wl-maz@kernel.org> <87lfabvzrz.fsf@nanos.tec.linutronix.de> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: tglx@linutronix.de, megha.dey@intel.com, linux-kernel@vger.kernel.org, dave.jiang@intel.com, ashok.raj@intel.com, kevin.tian@intel.com, dwmw@amazon.co.uk, x86@kernel.org, tony.luck@intel.com, dan.j.williams@intel.com, jgg@mellanox.com, kvm@vger.kernel.org, iommu@lists.linux-foundation.org, alex.williamson@redhat.com, bhelgaas@google.com, linux-pci@vger.kernel.org, baolu.lu@linux.intel.com, ravi.v.shankar@intel.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Thu, 25 Mar 2021 18:44:48 +0000, Thomas Gleixner wrote: > > On Thu, Mar 25 2021 at 17:08, Marc Zyngier wrote: > > Megha Dey wrote: > >> @@ -434,6 +434,12 @@ int __msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev, > >> if (ret) > >> return ret; > >> > >> + if (ops->msi_alloc_store) { > >> + ret = ops->msi_alloc_store(domain, dev, nvec); > > > > What is supposed to happen if we get aliasing devices (similar to what > > we have with devices behind a PCI bridge)? > > > > The ITS code goes through all kind of hoops to try and detect this > > case when sizing the translation tables (in the .prepare callback), > > and I have the feeling that sizing the message store is analogous. > > No. The message store itself is sized upfront by the underlying 'master' > device. Each 'master' device has it's own irqdomain. > > This is the allocation for the subdevice and this is not part of PCI and > therefore not subject to PCI aliasing. Fair enough. If we are guaranteed that there is no aliasing, then this point is moot. M. -- Without deviation from the norm, progress is not possible.