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From: Marc Zyngier <maz@kernel.org>
To: Jianjun Wang <jianjun.wang@mediatek.com>
Cc: "Bjorn Helgaas" <bhelgaas@google.com>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Ryder Lee" <ryder.lee@mediatek.com>,
	"Philipp Zabel" <p.zabel@pengutronix.de>,
	"Matthias Brugger" <matthias.bgg@gmail.com>,
	linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, youlin.pei@mediatek.com,
	chuanjia.liu@mediatek.com, qizhong.cheng@mediatek.com,
	sin_jieyang@mediatek.com, drinkcat@chromium.org,
	Rex-BC.Chen@mediatek.com, anson.chuang@mediatek.com,
	"Krzysztof Wilczyski" <kw@linux.com>,
	"Pali Rohár" <pali@kernel.org>
Subject: Re: [v9,5/7] PCI: mediatek-gen3: Add MSI support
Date: Wed, 24 Mar 2021 16:18:21 +0000	[thread overview]
Message-ID: <87wntwikz6.wl-maz@kernel.org> (raw)
In-Reply-To: <20210324030510.29177-6-jianjun.wang@mediatek.com>

On Wed, 24 Mar 2021 03:05:08 +0000,
Jianjun Wang <jianjun.wang@mediatek.com> wrote:
> 
> Add MSI support for MediaTek Gen3 PCIe controller.
> 
> This PCIe controller supports up to 256 MSI vectors, the MSI hardware
> block diagram is as follows:
> 
>                   +-----+
>                   | GIC |
>                   +-----+
>                      ^
>                      |
>                  port->irq
>                      |
>              +-+-+-+-+-+-+-+-+
>              |0|1|2|3|4|5|6|7| (PCIe intc)
>              +-+-+-+-+-+-+-+-+
>               ^ ^           ^
>               | |    ...    |
>       +-------+ +------+    +-----------+
>       |                |                |
> +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
> |0|1|...|30|31|  |0|1|...|30|31|  |0|1|...|30|31| (MSI sets)
> +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
>  ^ ^      ^  ^    ^ ^      ^  ^    ^ ^      ^  ^
>  | |      |  |    | |      |  |    | |      |  |  (MSI vectors)
>  | |      |  |    | |      |  |    | |      |  |
> 
>   (MSI SET0)       (MSI SET1)  ...   (MSI SET7)
> 
> With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
> each set has its own address for MSI message, and supports 32 MSI vectors
> to generate interrupt.
> 
> Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
> Acked-by: Ryder Lee <ryder.lee@mediatek.com>

Reviewed-by: Marc Zyngier <maz@kernel.org>

	M.

-- 
Without deviation from the norm, progress is not possible.

  reply	other threads:[~2021-03-24 16:19 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-24  3:05 [v9,0/7] PCI: mediatek: Add new generation controller support Jianjun Wang
2021-03-24  3:05 ` [v9,1/7] dt-bindings: PCI: mediatek-gen3: Add YAML schema Jianjun Wang
2021-03-24  3:05 ` [v9,2/7] PCI: Export pci_pio_to_address() for module use Jianjun Wang
2021-03-24  9:09   ` Pali Rohár
2021-04-13  9:53     ` Lorenzo Pieralisi
2021-04-16 19:24       ` Bjorn Helgaas
2021-03-24  3:05 ` [v9,3/7] PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192 Jianjun Wang
2021-04-08  5:45   ` Jianjun Wang
2021-03-24  3:05 ` [v9,4/7] PCI: mediatek-gen3: Add INTx support Jianjun Wang
2021-03-24 16:17   ` Marc Zyngier
2021-03-24  3:05 ` [v9,5/7] PCI: mediatek-gen3: Add MSI support Jianjun Wang
2021-03-24 16:18   ` Marc Zyngier [this message]
2021-03-27 19:28   ` Pali Rohár
2021-03-27 19:44     ` Marc Zyngier
2021-03-27 20:29       ` Pali Rohár
2021-03-27 21:45         ` Marc Zyngier
2021-03-24  3:05 ` [v9,6/7] PCI: mediatek-gen3: Add system PM support Jianjun Wang
2021-03-24  3:05 ` [v9,7/7] MAINTAINERS: Add Jianjun Wang as MediaTek PCI co-maintainer Jianjun Wang
2021-04-16 19:21 ` [v9,0/7] PCI: mediatek: Add new generation controller support Bjorn Helgaas
2021-04-19 10:44   ` Lorenzo Pieralisi
2021-04-20  2:05     ` Jianjun Wang

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