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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id f31-20020a056402329f00b0042617ba6381sm960602eda.11.2022.04.27.23.34.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 Apr 2022 23:34:25 -0700 (PDT) Message-ID: <918f5bc9-77f6-4d65-7432-ab53aadd6734@linaro.org> Date: Thu, 28 Apr 2022 08:34:24 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [RFC/RFT v2 03/11] dt-bindings: phy: rockchip: add PCIe v3 constants Content-Language: en-US To: Frank Wunderlich , linux-rockchip@lists.infradead.org Cc: Frank Wunderlich , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Kishon Vijay Abraham I , Vinod Koul , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Philipp Zabel , Johan Jonker , Peter Geis , Michael Riesch , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org References: <20220426132139.26761-1-linux@fw-web.de> <20220426132139.26761-4-linux@fw-web.de> From: Krzysztof Kozlowski In-Reply-To: <20220426132139.26761-4-linux@fw-web.de> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 26/04/2022 15:21, Frank Wunderlich wrote: > From: Frank Wunderlich > > Add constants that can be used in devicetree and driver for > PCIe v3 phy. > > Signed-off-by: Frank Wunderlich > --- > v2: > - new patch because splitting out this file > - rename file from snps to rockchip > --- > include/dt-bindings/phy/phy-rockchip-pcie3.h | 21 ++++++++++++++++++++ Naming - vendor,device. > 1 file changed, 21 insertions(+) > create mode 100644 include/dt-bindings/phy/phy-rockchip-pcie3.h > > diff --git a/include/dt-bindings/phy/phy-rockchip-pcie3.h b/include/dt-bindings/phy/phy-rockchip-pcie3.h > new file mode 100644 > index 000000000000..93e57edd337d > --- /dev/null > +++ b/include/dt-bindings/phy/phy-rockchip-pcie3.h > @@ -0,0 +1,21 @@ > +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ s/MIT/BSD-2-clause/ just like bindings because it is part of it. Unless you took it from something and it is already licensed like that? > +/* > + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. > + */ > + > +#ifndef _DT_BINDINGS_PHY_ROCKCHIP_PCIE3 > +#define _DT_BINDINGS_PHY_ROCKCHIP_PCIE3 > + > +/* > + * pcie30_phy_mode[2:0] > + * bit2: aggregation > + * bit1: bifurcation for port 1 > + * bit0: bifurcation for port 0 > + */ > +#define PHY_MODE_PCIE_AGGREGATION 4 /* PCIe3x4 */ > +#define PHY_MODE_PCIE_NANBNB 0 /* P1:PCIe3x2 + P0:PCIe3x2 */ > +#define PHY_MODE_PCIE_NANBBI 1 /* P1:PCIe3x2 + P0:PCIe3x1*2 */ > +#define PHY_MODE_PCIE_NABINB 2 /* P1:PCIe3x1*2 + P0:PCIe3x2 */ > +#define PHY_MODE_PCIE_NABIBI 3 /* P1:PCIe3x1*2 + P0:PCIe3x1*2 */ > + > +#endif /* _DT_BINDINGS_PHY_ROCKCHIP_PCIE3 */ Best regards, Krzysztof