From: Kishon Vijay Abraham I <kishon@ti.com>
To: Andrew Murray <andrew.murray@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Rob Herring <robh+dt@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-omap@vger.kernel.org>
Subject: Re: [PATCH 07/13] PCI: cadence: Add new *ops* for CPU addr fixup
Date: Thu, 19 Dec 2019 17:33:56 +0530 [thread overview]
Message-ID: <936cd6d6-33fc-6432-6fec-2b5173cb9ca4@ti.com> (raw)
In-Reply-To: <20191217124050.GD24359@e119886-lin.cambridge.arm.com>
Hi,
On 17/12/19 6:10 pm, Andrew Murray wrote:
> On Mon, Dec 09, 2019 at 02:51:41PM +0530, Kishon Vijay Abraham I wrote:
>> Cadence driver uses "mem" memory resource to obtain the offset of
>> configuration space address region, memory space address region and
>> message space address region. The obtained offset is used to program
>> the Address Translation Unit (ATU). However certain platforms like TI's
>> J721E SoC require the absolute address to be programmed in the ATU and not
>> just the offset.
>>
>> The same problem was solved in designware driver using a platform specific
>> ops for CPU addr fixup in commit a660083eb06c5bb0 ("PCI: dwc: designware:
>
> Thanks for this reference, though this doesn't need to be in the commit
> log, please put such comments underneath a ---.
>
>> Add new *ops* for CPU addr fixup"). Follow a similar mechanism in
>> Cadence too instead of directly using "mem" memory resource in Cadence
>> PCIe core.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>> .../pci/controller/cadence/pcie-cadence-host.c | 15 ++++-----------
>> drivers/pci/controller/cadence/pcie-cadence.c | 8 ++++++--
>> drivers/pci/controller/cadence/pcie-cadence.h | 1 +
>> 3 files changed, 11 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
>> index 2efc33b1cade..cf817be237af 100644
>> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
>> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
>> @@ -105,15 +105,14 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc)
>> static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
>> {
>> struct cdns_pcie *pcie = &rc->pcie;
>> - struct resource *mem_res = pcie->mem_res;
>> struct resource *bus_range = rc->bus_range;
>> struct resource *cfg_res = rc->cfg_res;
>> struct device *dev = pcie->dev;
>> struct device_node *np = dev->of_node;
>> struct of_pci_range_parser parser;
>> + u64 cpu_addr = cfg_res->start;
>> struct of_pci_range range;
>> u32 addr0, addr1, desc1;
>> - u64 cpu_addr;
>> int r, err;
>>
>> /*
>> @@ -126,7 +125,9 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
>> cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(0), addr1);
>> cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(0), desc1);
>>
>> - cpu_addr = cfg_res->start - mem_res->start;
>> + if (pcie->ops->cpu_addr_fixup)
>> + cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr);
>> +
>
> Won't this patch cause a breakage for existing users that won't have defined a
> cpu_addr_fixup? The offset isn't being calculated and so cpu_addr will be wrong?
Correct, this will need an additional patch in pcie-cadence-plat.c.
Thanks
Kishon
next prev parent reply other threads:[~2019-12-19 12:02 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-09 9:21 [PATCH 00/13] Add PCIe support to TI's J721E SoC Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 01/13] PCI: cadence: Remove stray "pm_runtime_put_sync()" in error path Kishon Vijay Abraham I
2019-12-16 13:45 ` Andrew Murray
2019-12-19 8:31 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 02/13] linux/kernel.h: Add PTR_ALIGN_DOWN macro Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 03/13] PCI: cadence: Add support to use custom read and write accessors Kishon Vijay Abraham I
2019-12-16 14:07 ` Andrew Murray
2019-12-19 11:41 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 04/13] PCI: cadence: Add support to start link and verify link status Kishon Vijay Abraham I
2019-12-17 11:58 ` Andrew Murray
2019-12-19 12:01 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 05/13] PCI: cadence: Add read and write accessors to perform only 32-bit accesses Kishon Vijay Abraham I
2019-12-09 21:15 ` Bjorn Helgaas
2019-12-16 14:49 ` Andrew Murray
2019-12-19 11:56 ` Kishon Vijay Abraham I
2019-12-19 12:03 ` Arnd Bergmann
2019-12-19 13:19 ` Kishon Vijay Abraham I
2019-12-19 20:16 ` Arnd Bergmann
2019-12-17 23:36 ` Bjorn Helgaas
2019-12-19 12:49 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 06/13] PCI: cadence: Allow pci_host_bridge to have custom pci_ops Kishon Vijay Abraham I
2019-12-17 12:32 ` Andrew Murray
2019-12-19 12:02 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 07/13] PCI: cadence: Add new *ops* for CPU addr fixup Kishon Vijay Abraham I
2019-12-17 12:40 ` Andrew Murray
2019-12-19 12:03 ` Kishon Vijay Abraham I [this message]
2019-12-09 9:21 ` [PATCH 08/13] PCI: cadence: Use local management register to configure Vendor ID Kishon Vijay Abraham I
2019-12-17 12:42 ` Andrew Murray
2019-12-19 12:12 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 09/13] dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC Kishon Vijay Abraham I
2019-12-19 0:08 ` Rob Herring
2019-12-19 13:13 ` Kishon Vijay Abraham I
2019-12-24 8:06 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 10/13] dt-bindings: PCI: Add EP " Kishon Vijay Abraham I
2019-12-19 0:14 ` Rob Herring
2019-12-19 13:14 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 11/13] PCI: j721e: Add TI J721E PCIe driver Kishon Vijay Abraham I
2019-12-17 14:23 ` Andrew Murray
2019-12-19 22:47 ` Bjorn Helgaas
2019-12-09 9:21 ` [PATCH 12/13] misc: pci_endpoint_test: Add J721E in pci_device_id table Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 13/13] MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe Kishon Vijay Abraham I
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