From: Xiaowei Bao <xiaowei.bao@nxp.com> To: Kishon Vijay Abraham I <kishon@ti.com>, Andrew Murray <andrew.murray@arm.com> Cc: "jingoohan1@gmail.com" <jingoohan1@gmail.com>, "gustavo.pimentel@synopsys.com" <gustavo.pimentel@synopsys.com>, "bhelgaas@google.com" <bhelgaas@google.com>, "robh+dt@kernel.org" <robh+dt@kernel.org>, "mark.rutland@arm.com" <mark.rutland@arm.com>, "shawnguo@kernel.org" <shawnguo@kernel.org>, Leo Li <leoyang.li@nxp.com>, "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>, "arnd@arndb.de" <arnd@arndb.de>, "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>, "M.h. Lian" <minghuan.lian@nxp.com>, Mingkai Hu <mingkai.hu@nxp.com>, "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>, "linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org>, "Z.q. Hou" <zhiqiang.hou@nxp.com> Subject: RE: [PATCH 02/10] PCI: designware-ep: Add the doorbell mode of MSI-X in EP mode Date: Fri, 16 Aug 2019 11:14:53 +0000 Message-ID: <AM5PR04MB3299ABCA78FB6B105F4BCDC7F5AF0@AM5PR04MB3299.eurprd04.prod.outlook.com> (raw) In-Reply-To: <02cf2f3d-336c-85bb-1fb5-a141c5a9cf79@ti.com> > -----Original Message----- > From: Kishon Vijay Abraham I <kishon@ti.com> > Sent: 2019年8月16日 18:50 > To: Xiaowei Bao <xiaowei.bao@nxp.com>; Andrew Murray > <andrew.murray@arm.com> > Cc: jingoohan1@gmail.com; gustavo.pimentel@synopsys.com; > bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com; > shawnguo@kernel.org; Leo Li <leoyang.li@nxp.com>; > lorenzo.pieralisi@arm.com; arnd@arndb.de; gregkh@linuxfoundation.org; > M.h. Lian <minghuan.lian@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; > linux-pci@vger.kernel.org; devicetree@vger.kernel.org; > linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > linuxppc-dev@lists.ozlabs.org; Z.q. Hou <zhiqiang.hou@nxp.com> > Subject: Re: [PATCH 02/10] PCI: designware-ep: Add the doorbell mode of > MSI-X in EP mode > > Hi, > > On 16/08/19 8:28 AM, Xiaowei Bao wrote: > > > > > >> -----Original Message----- > >> From: Andrew Murray <andrew.murray@arm.com> > >> Sent: 2019年8月15日 19:54 > >> To: Xiaowei Bao <xiaowei.bao@nxp.com> > >> Cc: jingoohan1@gmail.com; gustavo.pimentel@synopsys.com; > >> bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com; > >> shawnguo@kernel.org; Leo Li <leoyang.li@nxp.com>; kishon@ti.com; > >> lorenzo.pieralisi@arm.com; arnd@arndb.de; gregkh@linuxfoundation.org; > >> M.h. Lian <minghuan.lian@nxp.com>; Mingkai Hu > <mingkai.hu@nxp.com>; > >> Roy Zang <roy.zang@nxp.com>; linux-pci@vger.kernel.org; > >> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; > >> linux-arm-kernel@lists.infradead.org; linuxppc-dev@lists.ozlabs.org > >> Subject: Re: [PATCH 02/10] PCI: designware-ep: Add the doorbell mode > >> of MSI-X in EP mode > >> > >> On Thu, Aug 15, 2019 at 04:37:08PM +0800, Xiaowei Bao wrote: > >>> Add the doorbell mode of MSI-X in EP mode. > >>> > >>> Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> > >>> --- > >>> drivers/pci/controller/dwc/pcie-designware-ep.c | 14 > ++++++++++++++ > >>> drivers/pci/controller/dwc/pcie-designware.h | 14 > ++++++++++++++ > >>> 2 files changed, 28 insertions(+) > >>> > >>> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c > >>> b/drivers/pci/controller/dwc/pcie-designware-ep.c > >>> index 75e2955..e3a7cdf 100644 > >>> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c > >>> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c > >>> @@ -454,6 +454,20 @@ int dw_pcie_ep_raise_msi_irq(struct > dw_pcie_ep > >> *ep, u8 func_no, > >>> return 0; > >>> } > >>> > >>> +int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 > >> func_no, > >>> + u16 interrupt_num) > >>> +{ > >>> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); > >>> + u32 msg_data; > >>> + > >>> + msg_data = (func_no << PCIE_MSIX_DOORBELL_PF_SHIFT) | > >>> + (interrupt_num - 1); > >>> + > >>> + dw_pcie_writel_dbi(pci, PCIE_MSIX_DOORBELL, msg_data); > >>> + > >>> + return 0; > >>> +} > >>> + > >>> int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, > >>> u16 interrupt_num) > >> > >> Have I understood correctly that the hardware provides an alternative > >> mechanism that allows for raising MSI-X interrupts without the bother > >> of reading the capabilities registers? > > Yes, the hardware provide two way to MSI-X, please check the page 492 > > of > > DWC_pcie_dm_registers_4.30 Menu. > > MSIX_DOORBELL_OFF on page 492 0x948 Description: MSI-X Doorbell > > Register....> > >> > >> If so is there any good reason to keep dw_pcie_ep_raise_msix_irq? > >> (And thus use it in dw_plat_pcie_ep_raise_irq also)? > > I am not sure, but I think the dw_pcie_ep_raise_msix_irq function is > > not correct, because I think we can't get the MSIX table from the > > address ep->phys_base + tbl_addr, but I also don't know where I can get the > correct MSIX table. > > Sometime back when I tried raising MSI-X from EP, it was failing. It's quite > possible dw_pcie_ep_raise_msix_irq function is not correct. > > MSI-X table can be obtained from the inbound ATU corresponding to the MSIX > bar. > IMO MSI-X support in EP mode needs rework. For instance set_msix should > also take BAR number as input to be configured in the MSI-X capability. The > function driver (pci-epf-test.c) should allocate memory taking into account the > MSI-X table. Hi Kishon, Thanks a lot for your explain, yes, we can get the MSI-X table from the inbound ATU of the MSIX BAR. > > Thanks > Kishon
next prev parent reply index Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-08-15 8:37 [PATCH 01/10] PCI: designware-ep: Add multiple PFs support for DWC Xiaowei Bao 2019-08-15 8:37 ` [PATCH 02/10] PCI: designware-ep: Add the doorbell mode of MSI-X in EP mode Xiaowei Bao 2019-08-15 11:53 ` Andrew Murray 2019-08-16 2:58 ` Xiaowei Bao 2019-08-16 10:20 ` Andrew Murray 2019-08-16 11:01 ` Xiaowei Bao 2019-08-16 10:49 ` Kishon Vijay Abraham I 2019-08-16 11:14 ` Xiaowei Bao [this message] 2019-08-15 8:37 ` [PATCH 03/10] PCI: designware-ep: Move the function of getting MSI capability forward Xiaowei Bao 2019-08-15 8:37 ` [PATCH 04/10] dt-bindings: pci: layerscape-pci: add compatible strings for ls1088a and ls2088a Xiaowei Bao 2019-08-15 8:37 ` [PATCH 05/10] PCI: layerscape: Modify the way of getting capability with different PEX Xiaowei Bao 2019-08-15 12:51 ` Andrew Murray 2019-08-16 3:00 ` Xiaowei Bao 2019-08-16 10:25 ` Andrew Murray 2019-08-16 11:03 ` Xiaowei Bao 2019-08-15 8:37 ` [PATCH 06/10] PCI: layerscape: Modify the MSIX to the doorbell way Xiaowei Bao 2019-08-15 8:37 ` [PATCH 07/10] PCI: layerscape: Fix some format issue of the code Xiaowei Bao 2019-08-15 8:37 ` [PATCH 08/10] dt-bindings: PCI: Add the pf-offset property Xiaowei Bao 2019-08-27 16:26 ` Rob Herring 2019-08-15 8:37 ` [PATCH 09/10] arm64: dts: layerscape: Add PCIe EP node for ls1088a Xiaowei Bao 2019-08-15 8:37 ` [PATCH 10/10] misc: pci_endpoint_test: Add LS1088a in pci_device_id table Xiaowei Bao 2019-08-15 11:31 ` [PATCH 01/10] PCI: designware-ep: Add multiple PFs support for DWC Andrew Murray 2019-08-16 2:55 ` Xiaowei Bao 2019-08-16 9:44 ` Andrew Murray 2019-08-16 11:00 ` Xiaowei Bao 2019-08-16 12:35 ` Andrew Murray 2019-08-16 15:11 ` Xiaowei Bao
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