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From: "Z.q. Hou" <zhiqiang.hou@nxp.com>
To: Arnd Bergmann <arnd@arndb.de>
Cc: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"bhelgaas@google.com" <bhelgaas@google.com>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>,
	"l.subrahmanya@mobiveil.co.in" <l.subrahmanya@mobiveil.co.in>,
	"shawnguo@kernel.org" <shawnguo@kernel.org>,
	Leo Li <leoyang.li@nxp.com>,
	"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
	"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
	"will.deacon@arm.com" <will.deacon@arm.com>,
	Mingkai Hu <mingkai.hu@nxp.com>,
	"M.h. Lian" <minghuan.lian@nxp.com>,
	Xiaowei Bao <xiaowei.bao@nxp.com>
Subject: RE: [EXT] Re: [PATCHv5 4/6] PCI: mobiveil: Add PCIe Gen4 RC driver for NXP Layerscape SoCs
Date: Tue, 30 Apr 2019 00:26:40 +0000	[thread overview]
Message-ID: <AM6PR04MB57817E6C29731F6A96C3CAAB843A0@AM6PR04MB5781.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <CAK8P3a1rkBP4Hzy+=j8Ds_MoZU0K1_kh5YA0-ogOAG9TZ5fDNQ@mail.gmail.com>

Hi Arnd,

Thanks a lot for your comments!

> -----Original Message-----
> From: Arnd Bergmann [mailto:arnd@arndb.de]
> Sent: 2019年4月12日 22:42
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> <leoyang.li@nxp.com>; lorenzo.pieralisi@arm.com;
> catalin.marinas@arm.com; will.deacon@arm.com; Mingkai Hu
> <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>; Xiaowei Bao
> <xiaowei.bao@nxp.com>
> Subject: [EXT] Re: [PATCHv5 4/6] PCI: mobiveil: Add PCIe Gen4 RC driver for
> NXP Layerscape SoCs
> 
> WARNING: This email was created outside of NXP. DO NOT CLICK links or
> attachments unless you recognize the sender and know the content is safe.
> 
> 
> 
> > +       pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
> > +       if (!pcie)
> > +               return -ENOMEM;
> > +
> > +       mv_pci = devm_kzalloc(dev, sizeof(*mv_pci), GFP_KERNEL);
> > +       if (!mv_pci)
> > +               return -ENOMEM;
> > +
> 
> Just fold the two structures into one, and use pci_alloc_host_bridge() to
> allocate everything.

It's a good suggestion, will change in v6.

Thanks,
Zhiqiang

  reply	other threads:[~2019-04-30  0:27 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-12  9:52 [PATCHv5 0/6] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Z.q. Hou
2019-04-12  9:52 ` [PATCHv5 1/6] PCI: mobiveil: Refactor Mobiveil PCIe Host Bridge IP driver Z.q. Hou
2019-04-12 14:39   ` Arnd Bergmann
2019-04-30  0:23     ` [EXT] " Z.q. Hou
2019-04-24  5:35   ` Subrahmanya Lingappa
2019-04-30  1:12     ` [EXT] " Z.q. Hou
2019-04-12  9:52 ` [PATCHv5 2/6] PCI: mobiveil: Make mobiveil_host_init() can be used to re-init host Z.q. Hou
2019-04-12  9:52 ` [PATCHv5 3/6] dt-bindings: PCI: Add NXP Layerscape SoCs PCIe Gen4 controller Z.q. Hou
2019-04-12  9:52 ` [PATCHv5 4/6] PCI: mobiveil: Add PCIe Gen4 RC driver for NXP Layerscape SoCs Z.q. Hou
2019-04-12 14:00   ` Bjorn Helgaas
2019-04-14 11:16     ` [EXT] " Z.q. Hou
2019-04-12 14:41   ` Arnd Bergmann
2019-04-30  0:26     ` Z.q. Hou [this message]
2019-04-12  9:52 ` [PATCHv5 5/6] arm64: dts: lx2160a: Add PCIe controller DT nodes Z.q. Hou
2019-04-12  9:53 ` [PATCHv5 6/6] arm64: defconfig: Enable CONFIG_PCI_LAYERSCAPE_GEN4 Z.q. Hou

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