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From: Bharat Kumar Gogada <bharatku@xilinx.com>
To: Bharat Kumar Gogada <bharatku@xilinx.com>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Cc: "bhelgaas@google.com" <bhelgaas@google.com>
Subject: RE: [PATCH v3 1/2] PCI: xilinx-nwl: Enable coherent PCIe DMA traffic using CCI
Date: Mon, 15 Mar 2021 06:12:45 +0000	[thread overview]
Message-ID: <BYAPR02MB55590903AD09A045B8A345BFA56C9@BYAPR02MB5559.namprd02.prod.outlook.com> (raw)
In-Reply-To: <20210222084732.21521-1-bharat.kumar.gogada@xilinx.com>

Ping.

> -----Original Message-----
> From: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> Sent: Monday, February 22, 2021 2:18 PM
> To: linux-pci@vger.kernel.org; linux-kernel@vger.kernel.org
> Cc: bhelgaas@google.com; Bharat Kumar Gogada <bharatku@xilinx.com>
> Subject: [PATCH v3 1/2] PCI: xilinx-nwl: Enable coherent PCIe DMA traffic
> using CCI
> 
> Add support for routing PCIe DMA traffic coherently when Cache Coherent
> Interconnect (CCI) is enabled in the system.
> The "dma-coherent" property is used to determine if CCI is enabled or not.
> Refer to https://developer.arm.com/documentation/ddi0470/k/preface
> for the CCI specification.
> 
> Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> ---
>  drivers/pci/controller/pcie-xilinx-nwl.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c
> b/drivers/pci/controller/pcie-xilinx-nwl.c
> index 07e36661bbc2..8689311c5ef6 100644
> --- a/drivers/pci/controller/pcie-xilinx-nwl.c
> +++ b/drivers/pci/controller/pcie-xilinx-nwl.c
> @@ -26,6 +26,7 @@
> 
>  /* Bridge core config registers */
>  #define BRCFG_PCIE_RX0			0x00000000
> +#define BRCFG_PCIE_RX1			0x00000004
>  #define BRCFG_INTERRUPT			0x00000010
>  #define BRCFG_PCIE_RX_MSG_FILTER	0x00000020
> 
> @@ -128,6 +129,7 @@
>  #define NWL_ECAM_VALUE_DEFAULT		12
> 
>  #define CFG_DMA_REG_BAR			GENMASK(2, 0)
> +#define CFG_PCIE_CACHE			GENMASK(7, 0)
> 
>  #define INT_PCI_MSI_NR			(2 * 32)
> 
> @@ -675,6 +677,11 @@ static int nwl_pcie_bridge_init(struct nwl_pcie
> *pcie)
>  	nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,
>  			  BRCFG_PCIE_RX_MSG_FILTER);
> 
> +	/* This routes the PCIe DMA traffic to go through CCI path */
> +	if (of_dma_is_coherent(dev->of_node))
> +		nwl_bridge_writel(pcie, nwl_bridge_readl(pcie,
> BRCFG_PCIE_RX1) |
> +				  CFG_PCIE_CACHE, BRCFG_PCIE_RX1);
> +
>  	err = nwl_wait_for_link(pcie);
>  	if (err)
>  		return err;
> --
> 2.17.1


  parent reply	other threads:[~2021-03-15  6:13 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-22  8:47 [PATCH v3 1/2] PCI: xilinx-nwl: Enable coherent PCIe DMA traffic using CCI Bharat Kumar Gogada
2021-02-22  8:47 ` [PATCH v3 2/2] PCI: xilinx-nwl: Add optional "dma-coherent" property Bharat Kumar Gogada
2021-03-15  6:12 ` Bharat Kumar Gogada [this message]
2021-03-23 11:17   ` [PATCH v3 1/2] PCI: xilinx-nwl: Enable coherent PCIe DMA traffic using CCI Bharat Kumar Gogada
2021-04-02  5:31     ` Bharat Kumar Gogada
2021-04-06 14:20 ` Lorenzo Pieralisi
2021-04-06 20:34   ` Rob Herring
2021-04-07 16:01 ` Lorenzo Pieralisi
2021-04-08 15:58   ` Bharat Kumar Gogada

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