* [PATCH v6 1/8] dt-bindings: PCI: qcom: Convert to YAML
2022-05-06 15:20 [PATCH v6 0/8] dt-bindings: YAMLify pci/qcom,pcie schema Dmitry Baryshkov
@ 2022-05-06 15:21 ` Dmitry Baryshkov
2022-05-10 16:26 ` Rob Herring
2022-05-06 15:21 ` [PATCH v6 2/8] dt-bindings: PCI: qcom: Do not require resets on msm8996 platforms Dmitry Baryshkov
` (9 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Dmitry Baryshkov @ 2022-05-06 15:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi, Bjorn Helgaas,
Stanimir Varbanov, Manivannan Sadhasivam
Cc: Vinod Koul, linux-arm-msm, linux-pci, devicetree, Krzysztof Kozlowski
Changes to the schema:
- Fixed the ordering of clock-names/reset-names according to
the dtsi files.
- Mark vdda-supply as required only for apq/ipq8064 (as it was marked
as generally required in the txt file).
Changes to examples:
- Inline clock and reset numbers rather than including dt-bindings
files because of conflicts between the headers
- Split ranges and reg properties to follow current practice
- Change -gpio to -gpios
- Update IRQ flags to LEVEL_HIGH rater than NONE
- Removed extra "snps,dw-pcie" compatibility.
Note: while it was not clearly described in text schema, the majority of
Qualcomm platforms follow the snps,dw-pcie schema and use two
compatibility strings in the DT files: platform-specific one and a
fallback to the generic snps,dw-pcie one. However the platform itself is
not compatible with the snps,dw-pcie interface, so we are going to
remove it.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../devicetree/bindings/pci/qcom,pcie.txt | 398 ------------
.../devicetree/bindings/pci/qcom,pcie.yaml | 595 ++++++++++++++++++
2 files changed, 595 insertions(+), 398 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie.txt
create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie.yaml
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
deleted file mode 100644
index fd8b6d1912e7..000000000000
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ /dev/null
@@ -1,398 +0,0 @@
-* Qualcomm PCI express root complex
-
-- compatible:
- Usage: required
- Value type: <stringlist>
- Definition: Value should contain
- - "qcom,pcie-ipq8064" for ipq8064
- - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
- - "qcom,pcie-apq8064" for apq8064
- - "qcom,pcie-apq8084" for apq8084
- - "qcom,pcie-msm8996" for msm8996 or apq8096
- - "qcom,pcie-ipq4019" for ipq4019
- - "qcom,pcie-ipq8074" for ipq8074
- - "qcom,pcie-qcs404" for qcs404
- - "qcom,pcie-sc8180x" for sc8180x
- - "qcom,pcie-sdm845" for sdm845
- - "qcom,pcie-sm8150" for sm8150
- - "qcom,pcie-sm8250" for sm8250
- - "qcom,pcie-sm8450-pcie0" for PCIe0 on sm8450
- - "qcom,pcie-sm8450-pcie1" for PCIe1 on sm8450
- - "qcom,pcie-ipq6018" for ipq6018
-
-- reg:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Register ranges as listed in the reg-names property
-
-- reg-names:
- Usage: required
- Value type: <stringlist>
- Definition: Must include the following entries
- - "parf" Qualcomm specific registers
- - "dbi" DesignWare PCIe registers
- - "elbi" External local bus interface registers
- - "config" PCIe configuration space
- - "atu" ATU address space (optional)
-
-- device_type:
- Usage: required
- Value type: <string>
- Definition: Should be "pci". As specified in snps,dw-pcie.yaml
-
-- #address-cells:
- Usage: required
- Value type: <u32>
- Definition: Should be 3. As specified in snps,dw-pcie.yaml
-
-- #size-cells:
- Usage: required
- Value type: <u32>
- Definition: Should be 2. As specified in snps,dw-pcie.yaml
-
-- ranges:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: As specified in snps,dw-pcie.yaml
-
-- interrupts:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: MSI interrupt
-
-- interrupt-names:
- Usage: required
- Value type: <stringlist>
- Definition: Should contain "msi"
-
-- #interrupt-cells:
- Usage: required
- Value type: <u32>
- Definition: Should be 1. As specified in snps,dw-pcie.yaml
-
-- interrupt-map-mask:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: As specified in snps,dw-pcie.yaml
-
-- interrupt-map:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: As specified in snps,dw-pcie.yaml
-
-- clocks:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: List of phandle and clock specifier pairs as listed
- in clock-names property
-
-- clock-names:
- Usage: required
- Value type: <stringlist>
- Definition: Should contain the following entries
- - "iface" Configuration AHB clock
-
-- clock-names:
- Usage: required for ipq/apq8064
- Value type: <stringlist>
- Definition: Should contain the following entries
- - "core" Clocks the pcie hw block
- - "phy" Clocks the pcie PHY block
- - "aux" Clocks the pcie AUX block
- - "ref" Clocks the pcie ref block
-- clock-names:
- Usage: required for apq8084/ipq4019
- Value type: <stringlist>
- Definition: Should contain the following entries
- - "aux" Auxiliary (AUX) clock
- - "bus_master" Master AXI clock
- - "bus_slave" Slave AXI clock
-
-- clock-names:
- Usage: required for msm8996/apq8096
- Value type: <stringlist>
- Definition: Should contain the following entries
- - "pipe" Pipe Clock driving internal logic
- - "aux" Auxiliary (AUX) clock
- - "cfg" Configuration clock
- - "bus_master" Master AXI clock
- - "bus_slave" Slave AXI clock
-
-- clock-names:
- Usage: required for ipq8074
- Value type: <stringlist>
- Definition: Should contain the following entries
- - "iface" PCIe to SysNOC BIU clock
- - "axi_m" AXI Master clock
- - "axi_s" AXI Slave clock
- - "ahb" AHB clock
- - "aux" Auxiliary clock
-
-- clock-names:
- Usage: required for ipq6018
- Value type: <stringlist>
- Definition: Should contain the following entries
- - "iface" PCIe to SysNOC BIU clock
- - "axi_m" AXI Master clock
- - "axi_s" AXI Slave clock
- - "axi_bridge" AXI bridge clock
- - "rchng"
-
-- clock-names:
- Usage: required for qcs404
- Value type: <stringlist>
- Definition: Should contain the following entries
- - "iface" AHB clock
- - "aux" Auxiliary clock
- - "master_bus" AXI Master clock
- - "slave_bus" AXI Slave clock
-
-- clock-names:
- Usage: required for sdm845
- Value type: <stringlist>
- Definition: Should contain the following entries
- - "aux" Auxiliary clock
- - "cfg" Configuration clock
- - "bus_master" Master AXI clock
- - "bus_slave" Slave AXI clock
- - "slave_q2a" Slave Q2A clock
- - "tbu" PCIe TBU clock
- - "pipe" PIPE clock
-
-- clock-names:
- Usage: required for sc8180x, sm8150 and sm8250
- Value type: <stringlist>
- Definition: Should contain the following entries
- - "aux" Auxiliary clock
- - "cfg" Configuration clock
- - "bus_master" Master AXI clock
- - "bus_slave" Slave AXI clock
- - "slave_q2a" Slave Q2A clock
- - "tbu" PCIe TBU clock
- - "ddrss_sf_tbu" PCIe SF TBU clock
- - "pipe" PIPE clock
-
-- clock-names:
- Usage: required for sm8450-pcie0 and sm8450-pcie1
- Value type: <stringlist>
- Definition: Should contain the following entries
- - "aux" Auxiliary clock
- - "cfg" Configuration clock
- - "bus_master" Master AXI clock
- - "bus_slave" Slave AXI clock
- - "slave_q2a" Slave Q2A clock
- - "tbu" PCIe TBU clock
- - "ddrss_sf_tbu" PCIe SF TBU clock
- - "pipe" PIPE clock
- - "pipe_mux" PIPE MUX
- - "phy_pipe" PIPE output clock
- - "ref" REFERENCE clock
- - "aggre0" Aggre NoC PCIe0 AXI clock, only for sm8450-pcie0
- - "aggre1" Aggre NoC PCIe1 AXI clock
-
-- resets:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: List of phandle and reset specifier pairs as listed
- in reset-names property
-
-- reset-names:
- Usage: required for ipq/apq8064
- Value type: <stringlist>
- Definition: Should contain the following entries
- - "axi" AXI reset
- - "ahb" AHB reset
- - "por" POR reset
- - "pci" PCI reset
- - "phy" PHY reset
-
-- reset-names:
- Usage: required for apq8084
- Value type: <stringlist>
- Definition: Should contain the following entries
- - "core" Core reset
-
-- reset-names:
- Usage: required for ipq/apq8064
- Value type: <stringlist>
- Definition: Should contain the following entries
- - "axi_m" AXI master reset
- - "axi_s" AXI slave reset
- - "pipe" PIPE reset
- - "axi_m_vmid" VMID reset
- - "axi_s_xpu" XPU reset
- - "parf" PARF reset
- - "phy" PHY reset
- - "axi_m_sticky" AXI sticky reset
- - "pipe_sticky" PIPE sticky reset
- - "pwr" PWR reset
- - "ahb" AHB reset
- - "phy_ahb" PHY AHB reset
- - "ext" EXT reset
-
-- reset-names:
- Usage: required for ipq8074
- Value type: <stringlist>
- Definition: Should contain the following entries
- - "pipe" PIPE reset
- - "sleep" Sleep reset
- - "sticky" Core Sticky reset
- - "axi_m" AXI Master reset
- - "axi_s" AXI Slave reset
- - "ahb" AHB Reset
- - "axi_m_sticky" AXI Master Sticky reset
-
-- reset-names:
- Usage: required for ipq6018
- Value type: <stringlist>
- Definition: Should contain the following entries
- - "pipe" PIPE reset
- - "sleep" Sleep reset
- - "sticky" Core Sticky reset
- - "axi_m" AXI Master reset
- - "axi_s" AXI Slave reset
- - "ahb" AHB Reset
- - "axi_m_sticky" AXI Master Sticky reset
- - "axi_s_sticky" AXI Slave Sticky reset
-
-- reset-names:
- Usage: required for qcs404
- Value type: <stringlist>
- Definition: Should contain the following entries
- - "axi_m" AXI Master reset
- - "axi_s" AXI Slave reset
- - "axi_m_sticky" AXI Master Sticky reset
- - "pipe_sticky" PIPE sticky reset
- - "pwr" PWR reset
- - "ahb" AHB reset
-
-- reset-names:
- Usage: required for sc8180x, sdm845, sm8150, sm8250 and sm8450
- Value type: <stringlist>
- Definition: Should contain the following entries
- - "pci" PCIe core reset
-
-- power-domains:
- Usage: required for apq8084 and msm8996/apq8096
- Value type: <prop-encoded-array>
- Definition: A phandle and power domain specifier pair to the
- power domain which is responsible for collapsing
- and restoring power to the peripheral
-
-- vdda-supply:
- Usage: required
- Value type: <phandle>
- Definition: A phandle to the core analog power supply
-
-- vdda_phy-supply:
- Usage: required for ipq/apq8064
- Value type: <phandle>
- Definition: A phandle to the analog power supply for PHY
-
-- vdda_refclk-supply:
- Usage: required for ipq/apq8064
- Value type: <phandle>
- Definition: A phandle to the analog power supply for IC which generates
- reference clock
-- vddpe-3v3-supply:
- Usage: optional
- Value type: <phandle>
- Definition: A phandle to the PCIe endpoint power supply
-
-- phys:
- Usage: required for apq8084 and qcs404
- Value type: <phandle>
- Definition: List of phandle(s) as listed in phy-names property
-
-- phy-names:
- Usage: required for apq8084 and qcs404
- Value type: <stringlist>
- Definition: Should contain "pciephy"
-
-- <name>-gpios:
- Usage: optional
- Value type: <prop-encoded-array>
- Definition: List of phandle and GPIO specifier pairs. Should contain
- - "perst-gpios" PCIe endpoint reset signal line
- - "wake-gpios" PCIe endpoint wake signal line
-
-* Example for ipq/apq8064
- pcie@1b500000 {
- compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie";
- reg = <0x1b500000 0x1000
- 0x1b502000 0x80
- 0x1b600000 0x100
- 0x0ff00000 0x100000>;
- reg-names = "dbi", "elbi", "parf", "config";
- device_type = "pci";
- linux,pci-domain = <0>;
- bus-range = <0x00 0xff>;
- num-lanes = <1>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
- 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
- interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
- interrupt-names = "msi";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
- <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
- <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
- <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
- clocks = <&gcc PCIE_A_CLK>,
- <&gcc PCIE_H_CLK>,
- <&gcc PCIE_PHY_CLK>,
- <&gcc PCIE_AUX_CLK>,
- <&gcc PCIE_ALT_REF_CLK>;
- clock-names = "core", "iface", "phy", "aux", "ref";
- resets = <&gcc PCIE_ACLK_RESET>,
- <&gcc PCIE_HCLK_RESET>,
- <&gcc PCIE_POR_RESET>,
- <&gcc PCIE_PCI_RESET>,
- <&gcc PCIE_PHY_RESET>,
- <&gcc PCIE_EXT_RESET>;
- reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
- pinctrl-0 = <&pcie_pins_default>;
- pinctrl-names = "default";
- };
-
-* Example for apq8084
- pcie0@fc520000 {
- compatible = "qcom,pcie-apq8084", "snps,dw-pcie";
- reg = <0xfc520000 0x2000>,
- <0xff000000 0x1000>,
- <0xff001000 0x1000>,
- <0xff002000 0x2000>;
- reg-names = "parf", "dbi", "elbi", "config";
- device_type = "pci";
- linux,pci-domain = <0>;
- bus-range = <0x00 0xff>;
- num-lanes = <1>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges = <0x81000000 0 0 0xff200000 0 0x00100000 /* I/O */
- 0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */
- interrupts = <GIC_SPI 243 IRQ_TYPE_NONE>;
- interrupt-names = "msi";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
- <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
- <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
- <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
- clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
- <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
- <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
- <&gcc GCC_PCIE_0_AUX_CLK>;
- clock-names = "iface", "master_bus", "slave_bus", "aux";
- resets = <&gcc GCC_PCIE_0_BCR>;
- reset-names = "core";
- power-domains = <&gcc PCIE0_GDSC>;
- vdda-supply = <&pma8084_l3>;
- phys = <&pciephy0>;
- phy-names = "pciephy";
- perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>;
- pinctrl-0 = <&pcie0_pins_default>;
- pinctrl-names = "default";
- };
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
new file mode 100644
index 000000000000..16f765e96128
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -0,0 +1,595 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm PCI express root complex
+
+maintainers:
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+ - Stanimir Varbanov <svarbanov@mm-sol.com>
+
+description: |
+ Qualcomm PCIe root complex controller is bansed on the Synopsys DesignWare
+ PCIe IP.
+
+properties:
+ compatible:
+ enum:
+ - qcom,pcie-ipq8064
+ - qcom,pcie-ipq8064-v2
+ - qcom,pcie-apq8064
+ - qcom,pcie-apq8084
+ - qcom,pcie-msm8996
+ - qcom,pcie-ipq4019
+ - qcom,pcie-ipq8074
+ - qcom,pcie-qcs404
+ - qcom,pcie-sc8180x
+ - qcom,pcie-sdm845
+ - qcom,pcie-sm8150
+ - qcom,pcie-sm8250
+ - qcom,pcie-sm8450-pcie0
+ - qcom,pcie-sm8450-pcie1
+ - qcom,pcie-ipq6018
+
+ reg:
+ minItems: 4
+ maxItems: 5
+
+ reg-names:
+ minItems: 4
+ maxItems: 5
+ items:
+ enum:
+ - parf # Qualcomm specific registers
+ - dbi # DesignWare PCIe registers
+ - elbi # External local bus interface registers
+ - config # PCIe configuration space
+ - atu # ATU address space (optional)
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ items:
+ - const: msi
+
+ # Common definitions for clocks, clock-names and reset.
+ # Platform constraints are described later.
+ clocks:
+ minItems: 3
+ maxItems: 12
+
+ clock-names:
+ minItems: 3
+ maxItems: 12
+
+ resets:
+ minItems: 1
+ maxItems: 12
+
+ resets-names:
+ minItems: 1
+ maxItems: 12
+
+ vdda-supply:
+ description: A phandle to the core analog power supply
+
+ vdda_phy-supply:
+ description: A phandle to the core analog power supply for PHY
+
+ vdda_refclk-supply:
+ description: A phandle to the core analog power supply for IC which generates reference clock
+
+ vddpe-3v3-supply:
+ description: A phandle to the PCIe endpoint power supply
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ items:
+ - const: pciephy
+
+ power-domains:
+ maxItems: 1
+
+ perst-gpios:
+ description: GPIO controlled connection to PERST# signal
+ maxItems: 1
+
+ wake-gpios:
+ description: GPIO controlled connection to WAKE# signal
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+ - "#interrupt-cells"
+ - interrupt-map-mask
+ - interrupt-map
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-apq8064
+ - qcom,pcie-ipq8064
+ - qcom,pcie-ipq8064v2
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 5
+ clock-names:
+ minItems: 3
+ items:
+ - const: core # Clocks the pcie hw block
+ - const: iface # Configuration AHB clock
+ - const: phy # Clocks the pcie PHY block
+ - const: aux # Clocks the pcie AUX block, not on apq8064
+ - const: ref # Clocks the pcie ref block, not on apq8064
+ resets:
+ minItems: 5
+ maxItems: 6
+ reset-names:
+ minItems: 5
+ items:
+ - const: axi # AXI reset
+ - const: ahb # AHB reset
+ - const: por # POR reset
+ - const: pci # PCI reset
+ - const: phy # PHY reset
+ - const: ext # EXT reset, not on apq8064
+ required:
+ - vdda-supply
+ - vdda_phy-supply
+ - vdda_refclk-supply
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-apq8084
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ maxItems: 4
+ clock-names:
+ items:
+ - const: iface # Configuration AHB clock
+ - const: master_bus # Master AXI clock
+ - const: slave_bus # Slave AXI clock
+ - const: aux # Auxiliary (AUX) clock
+ resets:
+ maxItems: 1
+ reset-names:
+ items:
+ - const: core # Core reset
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-ipq4019
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 3
+ clock-names:
+ items:
+ - const: aux # Auxiliary (AUX) clock
+ - const: master_bus # Master AXI clock
+ - const: slave_bus # Slave AXI clock
+ resets:
+ minItems: 12
+ maxItems: 12
+ reset-names:
+ items:
+ - const: axi_m # AXI master reset
+ - const: axi_s # AXI slave reset
+ - const: pipe # PIPE reset
+ - const: axi_m_vmid # VMID reset
+ - const: axi_s_xpu # XPU reset
+ - const: parf # PARF reset
+ - const: phy # PHY reset
+ - const: axi_m_sticky # AXI sticky reset
+ - const: pipe_sticky # PIPE sticky reset
+ - const: pwr # PWR reset
+ - const: ahb # AHB reset
+ - const: phy_ahb # PHY AHB reset
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-msm8996
+ then:
+ oneOf:
+ - properties:
+ clock-names:
+ items:
+ - const: pipe # Pipe Clock driving internal logic
+ - const: aux # Auxiliary (AUX) clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - properties:
+ clock-names:
+ items:
+ - const: pipe # Pipe Clock driving internal logic
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: cfg # Configuration clock
+ - const: aux # Auxiliary (AUX) clock
+ properties:
+ clocks:
+ minItems: 5
+ maxItems: 5
+ resets: false
+ reset-names: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-ipq8074
+ then:
+ properties:
+ clocks:
+ minItems: 5
+ maxItems: 5
+ clock-names:
+ items:
+ - const: iface # PCIe to SysNOC BIU clock
+ - const: axi_m # AXI Master clock
+ - const: axi_s # AXI Slave clock
+ - const: ahb # AHB clock
+ - const: aux # Auxiliary clock
+ resets:
+ minItems: 7
+ maxItems: 7
+ reset-names:
+ items:
+ - const: pipe # PIPE reset
+ - const: sleep # Sleep reset
+ - const: sticky # Core Sticky reset
+ - const: axi_m # AXI Master reset
+ - const: axi_s # AXI Slave reset
+ - const: ahb # AHB Reset
+ - const: axi_m_sticky # AXI Master Sticky reset
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-ipq6018
+ then:
+ properties:
+ clocks:
+ minItems: 5
+ maxItems: 5
+ clock-names:
+ items:
+ - const: iface # PCIe to SysNOC BIU clock
+ - const: axi_m # AXI Master clock
+ - const: axi_s # AXI Slave clock
+ - const: axi_bridge # AXI bridge clock
+ - const: rchng
+ resets:
+ minItems: 8
+ maxItems: 8
+ reset-names:
+ items:
+ - const: pipe # PIPE reset
+ - const: sleep # Sleep reset
+ - const: sticky # Core Sticky reset
+ - const: axi_m # AXI Master reset
+ - const: axi_s # AXI Slave reset
+ - const: ahb # AHB Reset
+ - const: axi_m_sticky # AXI Master Sticky reset
+ - const: axi_s_sticky # AXI Slave Sticky reset
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-qcs404
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ maxItems: 4
+ clock-names:
+ items:
+ - const: iface # AHB clock
+ - const: aux # Auxiliary clock
+ - const: master_bus # AXI Master clock
+ - const: slave_bus # AXI Slave clock
+ resets:
+ minItems: 6
+ maxItems: 6
+ reset-names:
+ items:
+ - const: axi_m # AXI Master reset
+ - const: axi_s # AXI Slave reset
+ - const: axi_m_sticky # AXI Master Sticky reset
+ - const: pipe_sticky # PIPE sticky reset
+ - const: pwr # PWR reset
+ - const: ahb # AHB reset
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-sdm845
+ then:
+ oneOf:
+ # Unfortunately the "optional" ref clock is used in the middle of the list
+ - properties:
+ clocks:
+ minItems: 8
+ maxItems: 8
+ clock-names:
+ items:
+ - const: pipe # PIPE clock
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: ref # REFERENCE clock
+ - const: tbu # PCIe TBU clock
+ - properties:
+ clocks:
+ minItems: 7
+ maxItems: 7
+ clock-names:
+ items:
+ - const: pipe # PIPE clock
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: tbu # PCIe TBU clock
+ properties:
+ resets:
+ maxItems: 1
+ reset-names:
+ items:
+ - const: pci # PCIe core reset
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-sc8180x
+ - qcom,pcie-sm8150
+ - qcom,pcie-sm8250
+ then:
+ oneOf:
+ # Unfortunately the "optional" ref clock is used in the middle of the list
+ - properties:
+ clocks:
+ minItems: 9
+ maxItems: 9
+ clock-names:
+ items:
+ - const: pipe # PIPE clock
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: ref # REFERENCE clock
+ - const: tbu # PCIe TBU clock
+ - const: ddrss_sf_tbu # PCIe SF TBU clock
+ - properties:
+ clocks:
+ minItems: 8
+ maxItems: 8
+ clock-names:
+ items:
+ - const: pipe # PIPE clock
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: tbu # PCIe TBU clock
+ - const: ddrss_sf_tbu # PCIe SF TBU clock
+ properties:
+ resets:
+ maxItems: 1
+ reset-names:
+ items:
+ - const: pci # PCIe core reset
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-sm8450-pcie0
+ then:
+ properties:
+ clocks:
+ minItems: 12
+ maxItems: 12
+ clock-names:
+ items:
+ - const: pipe # PIPE clock
+ - const: pipe_mux # PIPE MUX
+ - const: phy_pipe # PIPE output clock
+ - const: ref # REFERENCE clock
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: ddrss_sf_tbu # PCIe SF TBU clock
+ - const: aggre0 # Aggre NoC PCIe0 AXI clock
+ - const: aggre1 # Aggre NoC PCIe1 AXI clock
+ resets:
+ maxItems: 1
+ reset-names:
+ items:
+ - const: pci # PCIe core reset
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-sm8450-pcie1
+ then:
+ properties:
+ clocks:
+ minItems: 11
+ maxItems: 11
+ clock-names:
+ items:
+ - const: pipe # PIPE clock
+ - const: pipe_mux # PIPE MUX
+ - const: phy_pipe # PIPE output clock
+ - const: ref # REFERENCE clock
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: ddrss_sf_tbu # PCIe SF TBU clock
+ - const: aggre1 # Aggre NoC PCIe1 AXI clock
+ resets:
+ maxItems: 1
+ reset-names:
+ items:
+ - const: pci # PCIe core reset
+
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-apq8064
+ - qcom,pcie-ipq4019
+ - qcom,pcie-ipq8064
+ - qcom,pcie-ipq8064v2
+ - qcom,pcie-ipq8074
+ - qcom,pcie-qcs404
+ then:
+ required:
+ - power-domains
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ pcie@1b500000 {
+ compatible = "qcom,pcie-ipq8064";
+ reg = <0x1b500000 0x1000>,
+ <0x1b502000 0x80>,
+ <0x1b600000 0x100>,
+ <0x0ff00000 0x100000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>,
+ <0x82000000 0 0 0x08000000 0 0x07e00000>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc 41>,
+ <&gcc 43>,
+ <&gcc 44>,
+ <&gcc 42>,
+ <&gcc 248>;
+ clock-names = "core", "iface", "phy", "aux", "ref";
+ resets = <&gcc 27>,
+ <&gcc 26>,
+ <&gcc 25>,
+ <&gcc 24>,
+ <&gcc 23>,
+ <&gcc 22>;
+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
+ pinctrl-0 = <&pcie_pins_default>;
+ pinctrl-names = "default";
+ vdda-supply = <&pm8921_s3>;
+ vdda_phy-supply = <&pm8921_lvs6>;
+ vdda_refclk-supply = <&ext_3p3v>;
+ };
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/gpio/gpio.h>
+ pcie@fc520000 {
+ compatible = "qcom,pcie-apq8084";
+ reg = <0xfc520000 0x2000>,
+ <0xff000000 0x1000>,
+ <0xff001000 0x1000>,
+ <0xff002000 0x2000>;
+ reg-names = "parf", "dbi", "elbi", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x81000000 0 0 0xff200000 0 0x00100000>,
+ <0x82000000 0 0x00300000 0xff300000 0 0x00d00000>;
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc 324>,
+ <&gcc 325>,
+ <&gcc 327>,
+ <&gcc 323>;
+ clock-names = "iface", "master_bus", "slave_bus", "aux";
+ resets = <&gcc 81>;
+ reset-names = "core";
+ power-domains = <&gcc 1>;
+ vdda-supply = <&pma8084_l3>;
+ phys = <&pciephy0>;
+ phy-names = "pciephy";
+ perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&pcie0_pins_default>;
+ pinctrl-names = "default";
+ };
+...
--
2.35.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v6 1/8] dt-bindings: PCI: qcom: Convert to YAML
2022-05-06 15:21 ` [PATCH v6 1/8] dt-bindings: PCI: qcom: Convert to YAML Dmitry Baryshkov
@ 2022-05-10 16:26 ` Rob Herring
0 siblings, 0 replies; 21+ messages in thread
From: Rob Herring @ 2022-05-10 16:26 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Lorenzo Pieralisi, linux-arm-msm, Manivannan Sadhasivam,
Bjorn Helgaas, Rob Herring, Gustavo Pimentel, Bjorn Andersson,
linux-pci, devicetree, Krzysztof Kozlowski, Vinod Koul,
Krzysztof Kozlowski, Stanimir Varbanov, Jingoo Han, Andy Gross
On Fri, 06 May 2022 18:21:00 +0300, Dmitry Baryshkov wrote:
> Changes to the schema:
> - Fixed the ordering of clock-names/reset-names according to
> the dtsi files.
> - Mark vdda-supply as required only for apq/ipq8064 (as it was marked
> as generally required in the txt file).
>
> Changes to examples:
> - Inline clock and reset numbers rather than including dt-bindings
> files because of conflicts between the headers
> - Split ranges and reg properties to follow current practice
> - Change -gpio to -gpios
> - Update IRQ flags to LEVEL_HIGH rater than NONE
> - Removed extra "snps,dw-pcie" compatibility.
>
> Note: while it was not clearly described in text schema, the majority of
> Qualcomm platforms follow the snps,dw-pcie schema and use two
> compatibility strings in the DT files: platform-specific one and a
> fallback to the generic snps,dw-pcie one. However the platform itself is
> not compatible with the snps,dw-pcie interface, so we are going to
> remove it.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../devicetree/bindings/pci/qcom,pcie.txt | 398 ------------
> .../devicetree/bindings/pci/qcom,pcie.yaml | 595 ++++++++++++++++++
> 2 files changed, 595 insertions(+), 398 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie.txt
> create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v6 2/8] dt-bindings: PCI: qcom: Do not require resets on msm8996 platforms
2022-05-06 15:20 [PATCH v6 0/8] dt-bindings: YAMLify pci/qcom,pcie schema Dmitry Baryshkov
2022-05-06 15:21 ` [PATCH v6 1/8] dt-bindings: PCI: qcom: Convert to YAML Dmitry Baryshkov
@ 2022-05-06 15:21 ` Dmitry Baryshkov
2022-05-10 16:46 ` Rob Herring
2022-05-06 15:21 ` [PATCH v6 3/8] dt-bindings: PCI: qcom: Specify reg-names explicitly Dmitry Baryshkov
` (8 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Dmitry Baryshkov @ 2022-05-06 15:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi, Bjorn Helgaas,
Stanimir Varbanov, Manivannan Sadhasivam
Cc: Vinod Koul, linux-arm-msm, linux-pci, devicetree, Krzysztof Kozlowski
On MSM8996/APQ8096 platforms the PCIe controller doesn't have any
resets. So move the requirement stanza under the corresponding if
condition.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../devicetree/bindings/pci/qcom,pcie.yaml | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index 16f765e96128..ce4f53cdaba0 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -114,8 +114,6 @@ required:
- interrupt-map
- clocks
- clock-names
- - resets
- - reset-names
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
@@ -504,6 +502,18 @@ allOf:
required:
- power-domains
+ - if:
+ not:
+ properties:
+ compatibles:
+ contains:
+ enum:
+ - qcom,pcie-msm8996
+ then:
+ required:
+ - resets
+ - reset-names
+
unevaluatedProperties: false
examples:
--
2.35.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v6 2/8] dt-bindings: PCI: qcom: Do not require resets on msm8996 platforms
2022-05-06 15:21 ` [PATCH v6 2/8] dt-bindings: PCI: qcom: Do not require resets on msm8996 platforms Dmitry Baryshkov
@ 2022-05-10 16:46 ` Rob Herring
0 siblings, 0 replies; 21+ messages in thread
From: Rob Herring @ 2022-05-10 16:46 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Stanimir Varbanov, Manivannan Sadhasivam, Jingoo Han,
Rob Herring, Lorenzo Pieralisi, linux-arm-msm, Gustavo Pimentel,
Bjorn Helgaas, linux-pci, Krzysztof Kozlowski, Bjorn Andersson,
Krzysztof Kozlowski, Andy Gross, devicetree, Vinod Koul
On Fri, 06 May 2022 18:21:01 +0300, Dmitry Baryshkov wrote:
> On MSM8996/APQ8096 platforms the PCIe controller doesn't have any
> resets. So move the requirement stanza under the corresponding if
> condition.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../devicetree/bindings/pci/qcom,pcie.yaml | 14 ++++++++++++--
> 1 file changed, 12 insertions(+), 2 deletions(-)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v6 3/8] dt-bindings: PCI: qcom: Specify reg-names explicitly
2022-05-06 15:20 [PATCH v6 0/8] dt-bindings: YAMLify pci/qcom,pcie schema Dmitry Baryshkov
2022-05-06 15:21 ` [PATCH v6 1/8] dt-bindings: PCI: qcom: Convert to YAML Dmitry Baryshkov
2022-05-06 15:21 ` [PATCH v6 2/8] dt-bindings: PCI: qcom: Do not require resets on msm8996 platforms Dmitry Baryshkov
@ 2022-05-06 15:21 ` Dmitry Baryshkov
2022-05-10 16:48 ` Rob Herring
2022-05-06 15:21 ` [PATCH v6 4/8] dt-bindings: PCI: qcom: Add schema for sc7280 chipset Dmitry Baryshkov
` (7 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Dmitry Baryshkov @ 2022-05-06 15:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi, Bjorn Helgaas,
Stanimir Varbanov, Manivannan Sadhasivam
Cc: Vinod Koul, linux-arm-msm, linux-pci, devicetree, Krzysztof Kozlowski
Instead of specifying the enum of possible reg-names, specify them
explicitly. This allows us to specify which chipsets need the "atu"
regions, which do not. Also it clearly describes which platforms
enumerate PCIe cores using the dbi region and which use parf region for
that.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../devicetree/bindings/pci/qcom,pcie.yaml | 91 +++++++++++++++++--
1 file changed, 84 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index ce4f53cdaba0..e91ae436cafe 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -40,13 +40,6 @@ properties:
reg-names:
minItems: 4
maxItems: 5
- items:
- enum:
- - parf # Qualcomm specific registers
- - dbi # DesignWare PCIe registers
- - elbi # External local bus interface registers
- - config # PCIe configuration space
- - atu # ATU address space (optional)
interrupts:
maxItems: 1
@@ -117,6 +110,90 @@ required:
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-apq8064
+ - qcom,pcie-ipq4019
+ - qcom,pcie-ipq8064
+ - qcom,pcie-ipq8064v2
+ - qcom,pcie-ipq8074
+ - qcom,pcie-qcs404
+ then:
+ properties:
+ reg:
+ minItems: 4
+ maxItems: 4
+ reg-names:
+ items:
+ - const: dbi # DesignWare PCIe registers
+ - const: elbi # External local bus interface registers
+ - const: parf # Qualcomm specific registers
+ - const: config # PCIe configuration space
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-ipq6018
+ then:
+ properties:
+ reg:
+ minItems: 5
+ maxItems: 5
+ reg-names:
+ items:
+ - const: dbi # DesignWare PCIe registers
+ - const: elbi # External local bus interface registers
+ - const: atu # ATU address space
+ - const: parf # Qualcomm specific registers
+ - const: config # PCIe configuration space
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-apq8084
+ - qcom,pcie-msm8996
+ - qcom,pcie-sdm845
+ then:
+ properties:
+ reg:
+ minItems: 4
+ maxItems: 4
+ reg-names:
+ items:
+ - const: parf # Qualcomm specific registers
+ - const: dbi # DesignWare PCIe registers
+ - const: elbi # External local bus interface registers
+ - const: config # PCIe configuration space
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-sc8180x
+ - qcom,pcie-sm8250
+ - qcom,pcie-sm8450-pcie0
+ - qcom,pcie-sm8450-pcie1
+ then:
+ properties:
+ reg:
+ minItems: 5
+ maxItems: 5
+ reg-names:
+ items:
+ - const: parf # Qualcomm specific registers
+ - const: dbi # DesignWare PCIe registers
+ - const: elbi # External local bus interface registers
+ - const: atu # ATU address space
+ - const: config # PCIe configuration space
+
- if:
properties:
compatible:
--
2.35.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v6 3/8] dt-bindings: PCI: qcom: Specify reg-names explicitly
2022-05-06 15:21 ` [PATCH v6 3/8] dt-bindings: PCI: qcom: Specify reg-names explicitly Dmitry Baryshkov
@ 2022-05-10 16:48 ` Rob Herring
0 siblings, 0 replies; 21+ messages in thread
From: Rob Herring @ 2022-05-10 16:48 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Stanimir Varbanov, devicetree, Andy Gross, Lorenzo Pieralisi,
Jingoo Han, Rob Herring, linux-arm-msm, Vinod Koul,
Bjorn Andersson, Krzysztof Kozlowski, Krzysztof Kozlowski,
linux-pci, Manivannan Sadhasivam, Bjorn Helgaas,
Gustavo Pimentel
On Fri, 06 May 2022 18:21:02 +0300, Dmitry Baryshkov wrote:
> Instead of specifying the enum of possible reg-names, specify them
> explicitly. This allows us to specify which chipsets need the "atu"
> regions, which do not. Also it clearly describes which platforms
> enumerate PCIe cores using the dbi region and which use parf region for
> that.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../devicetree/bindings/pci/qcom,pcie.yaml | 91 +++++++++++++++++--
> 1 file changed, 84 insertions(+), 7 deletions(-)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v6 4/8] dt-bindings: PCI: qcom: Add schema for sc7280 chipset
2022-05-06 15:20 [PATCH v6 0/8] dt-bindings: YAMLify pci/qcom,pcie schema Dmitry Baryshkov
` (2 preceding siblings ...)
2022-05-06 15:21 ` [PATCH v6 3/8] dt-bindings: PCI: qcom: Specify reg-names explicitly Dmitry Baryshkov
@ 2022-05-06 15:21 ` Dmitry Baryshkov
2022-05-10 16:50 ` Rob Herring
2022-05-06 15:21 ` [PATCH v6 5/8] arm64: dts: qcom: stop using snps,dw-pcie falback Dmitry Baryshkov
` (6 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Dmitry Baryshkov @ 2022-05-06 15:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi, Bjorn Helgaas,
Stanimir Varbanov, Manivannan Sadhasivam
Cc: Vinod Koul, linux-arm-msm, linux-pci, devicetree, Krzysztof Kozlowski
Add support for sc7280-specific clock and reset definitions.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../devicetree/bindings/pci/qcom,pcie.yaml | 32 +++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index e91ae436cafe..0b69b12b849e 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -25,6 +25,7 @@ properties:
- qcom,pcie-ipq4019
- qcom,pcie-ipq8074
- qcom,pcie-qcs404
+ - qcom,pcie-sc7280
- qcom,pcie-sc8180x
- qcom,pcie-sdm845
- qcom,pcie-sm8150
@@ -177,6 +178,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,pcie-sc7280
- qcom,pcie-sc8180x
- qcom,pcie-sm8250
- qcom,pcie-sm8450-pcie0
@@ -412,6 +414,36 @@ allOf:
- const: pwr # PWR reset
- const: ahb # AHB reset
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-sc7280
+ then:
+ properties:
+ clocks:
+ minItems: 11
+ maxItems: 11
+ clock-names:
+ items:
+ - const: pipe # PIPE clock
+ - const: pipe_mux # PIPE MUX
+ - const: phy_pipe # PIPE output clock
+ - const: ref # REFERENCE clock
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: tbu # PCIe TBU clock
+ - const: ddrss_sf_tbu # PCIe SF TBU clock
+ resets:
+ maxItems: 1
+ reset-names:
+ items:
+ - const: pci # PCIe core reset
+
- if:
properties:
compatible:
--
2.35.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v6 4/8] dt-bindings: PCI: qcom: Add schema for sc7280 chipset
2022-05-06 15:21 ` [PATCH v6 4/8] dt-bindings: PCI: qcom: Add schema for sc7280 chipset Dmitry Baryshkov
@ 2022-05-10 16:50 ` Rob Herring
0 siblings, 0 replies; 21+ messages in thread
From: Rob Herring @ 2022-05-10 16:50 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Gustavo Pimentel, Manivannan Sadhasivam, linux-arm-msm,
Andy Gross, Stanimir Varbanov, Krzysztof Kozlowski, devicetree,
Krzysztof Kozlowski, Bjorn Helgaas, Jingoo Han, Vinod Koul,
linux-pci, Bjorn Andersson, Rob Herring, Lorenzo Pieralisi
On Fri, 06 May 2022 18:21:03 +0300, Dmitry Baryshkov wrote:
> Add support for sc7280-specific clock and reset definitions.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../devicetree/bindings/pci/qcom,pcie.yaml | 32 +++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v6 5/8] arm64: dts: qcom: stop using snps,dw-pcie falback
2022-05-06 15:20 [PATCH v6 0/8] dt-bindings: YAMLify pci/qcom,pcie schema Dmitry Baryshkov
` (3 preceding siblings ...)
2022-05-06 15:21 ` [PATCH v6 4/8] dt-bindings: PCI: qcom: Add schema for sc7280 chipset Dmitry Baryshkov
@ 2022-05-06 15:21 ` Dmitry Baryshkov
2022-05-06 15:21 ` [PATCH v6 6/8] arm: " Dmitry Baryshkov
` (5 subsequent siblings)
10 siblings, 0 replies; 21+ messages in thread
From: Dmitry Baryshkov @ 2022-05-06 15:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi, Bjorn Helgaas,
Stanimir Varbanov, Manivannan Sadhasivam
Cc: Vinod Koul, linux-arm-msm, linux-pci, devicetree, Krzysztof Kozlowski
Qualcomm PCIe devices are not really compatible with the snps,dw-pcie.
Unlike the generic IP core, they have special requirements regarding
enabling clocks, toggling resets, using the PHY, etc.
This is not to mention that platform snps-dw-pcie driver expects to find
two IRQs declared, while Qualcomm platforms use just one.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 6 +++---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 +++---
4 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index f0f81c23c16f..b577b9046938 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1574,7 +1574,7 @@ agnoc@0 {
ranges;
pcie0: pcie@600000 {
- compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
+ compatible = "qcom,pcie-msm8996";
status = "disabled";
power-domains = <&gcc PCIE0_GDSC>;
bus-range = <0x00 0xff>;
@@ -1626,7 +1626,7 @@ pcie0: pcie@600000 {
};
pcie1: pcie@608000 {
- compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
+ compatible = "qcom,pcie-msm8996";
power-domains = <&gcc PCIE1_GDSC>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
@@ -1679,7 +1679,7 @@ pcie1: pcie@608000 {
};
pcie2: pcie@610000 {
- compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
+ compatible = "qcom,pcie-msm8996";
power-domains = <&gcc PCIE2_GDSC>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 3f06f7cd3cf2..2386081463e3 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -1280,7 +1280,7 @@ glink-edge {
};
pcie: pci@10000000 {
- compatible = "qcom,pcie-qcs404", "snps,dw-pcie";
+ compatible = "qcom,pcie-qcs404";
reg = <0x10000000 0xf1d>,
<0x10000f20 0xa8>,
<0x07780000 0x2000>,
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index b31bf62e8680..85dfa0842003 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2027,7 +2027,7 @@ llcc: system-cache-controller@1100000 {
};
pcie0: pci@1c00000 {
- compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
+ compatible = "qcom,pcie-sdm845";
reg = <0 0x01c00000 0 0x2000>,
<0 0x60000000 0 0xf1d>,
<0 0x60000f20 0 0xa8>,
@@ -2132,7 +2132,7 @@ pcie0_lane: phy@1c06200 {
};
pcie1: pci@1c08000 {
- compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
+ compatible = "qcom,pcie-sdm845";
reg = <0 0x01c08000 0 0x2000>,
<0 0x40000000 0 0xf1d>,
<0 0x40000f20 0 0xa8>,
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index af8f22636436..410272a1e19b 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -1789,7 +1789,7 @@ mmss_noc: interconnect@1740000 {
};
pcie0: pci@1c00000 {
- compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
+ compatible = "qcom,pcie-sm8250";
reg = <0 0x01c00000 0 0x3000>,
<0 0x60000000 0 0xf1d>,
<0 0x60000f20 0 0xa8>,
@@ -1888,7 +1888,7 @@ pcie0_lane: phy@1c06200 {
};
pcie1: pci@1c08000 {
- compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
+ compatible = "qcom,pcie-sm8250";
reg = <0 0x01c08000 0 0x3000>,
<0 0x40000000 0 0xf1d>,
<0 0x40000f20 0 0xa8>,
@@ -1994,7 +1994,7 @@ pcie1_lane: phy@1c0e200 {
};
pcie2: pci@1c10000 {
- compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
+ compatible = "qcom,pcie-sm8250";
reg = <0 0x01c10000 0 0x3000>,
<0 0x64000000 0 0xf1d>,
<0 0x64000f20 0 0xa8>,
--
2.35.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v6 6/8] arm: dts: qcom: stop using snps,dw-pcie falback
2022-05-06 15:20 [PATCH v6 0/8] dt-bindings: YAMLify pci/qcom,pcie schema Dmitry Baryshkov
` (4 preceding siblings ...)
2022-05-06 15:21 ` [PATCH v6 5/8] arm64: dts: qcom: stop using snps,dw-pcie falback Dmitry Baryshkov
@ 2022-05-06 15:21 ` Dmitry Baryshkov
2022-05-06 15:21 ` [PATCH v6 7/8] arm: dts: qcom-*: replace deprecated perst-gpio with perst-gpios Dmitry Baryshkov
` (4 subsequent siblings)
10 siblings, 0 replies; 21+ messages in thread
From: Dmitry Baryshkov @ 2022-05-06 15:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi, Bjorn Helgaas,
Stanimir Varbanov, Manivannan Sadhasivam
Cc: Vinod Koul, linux-arm-msm, linux-pci, devicetree, Krzysztof Kozlowski
Qualcomm PCIe devices are not really compatible with the snps,dw-pcie.
Unlike the generic IP core, they have special requirements regarding
enabling clocks, toggling resets, using the PHY, etc.
This is not to mention that platform snps-dw-pcie driver expects to find
two IRQs declared, while Qualcomm platforms use just one.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 2 +-
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index a1c8ae516d21..ec2f98671a8c 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -1370,7 +1370,7 @@ gfx3d1: iommu@7d00000 {
};
pcie: pci@1b500000 {
- compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
+ compatible = "qcom,pcie-apq8064";
reg = <0x1b500000 0x1000>,
<0x1b502000 0x80>,
<0x1b600000 0x100>,
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index a9d0566a3190..1e814dbe135e 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -412,7 +412,7 @@ restart@4ab000 {
};
pcie0: pci@40000000 {
- compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
+ compatible = "qcom,pcie-ipq4019";
reg = <0x40000000 0xf1d
0x40000f20 0xa8
0x80000 0x2000
--
2.35.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v6 7/8] arm: dts: qcom-*: replace deprecated perst-gpio with perst-gpios
2022-05-06 15:20 [PATCH v6 0/8] dt-bindings: YAMLify pci/qcom,pcie schema Dmitry Baryshkov
` (5 preceding siblings ...)
2022-05-06 15:21 ` [PATCH v6 6/8] arm: " Dmitry Baryshkov
@ 2022-05-06 15:21 ` Dmitry Baryshkov
2022-05-06 15:21 ` [PATCH v6 8/8] arm64: dts: qcom: " Dmitry Baryshkov
` (3 subsequent siblings)
10 siblings, 0 replies; 21+ messages in thread
From: Dmitry Baryshkov @ 2022-05-06 15:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi, Bjorn Helgaas,
Stanimir Varbanov, Manivannan Sadhasivam
Cc: Vinod Koul, linux-arm-msm, linux-pci, devicetree, Krzysztof Kozlowski
Replace deprecated perst-gpio properties with up-to-date perst-gpios
in the arm32 Qualcomm Snapdragon device trees.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts | 2 +-
arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 2 +-
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 2 +-
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 2 +-
arch/arm/boot/dts/qcom-ipq8064.dtsi | 6 +++---
5 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
index e068a8d0adf0..160291c5ebeb 100644
--- a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
@@ -215,7 +215,7 @@ pci@1b500000 {
vdda_refclk-supply = <&v3p3_fixed>;
pinctrl-0 = <&pcie_pins>;
pinctrl-names = "default";
- perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>;
+ perst-gpios = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>;
};
amba {
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index 2638b380be20..8b1d540a5f65 100644
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -285,7 +285,7 @@ pci@1b500000 {
vdda_refclk-supply = <&ext_3p3v>;
pinctrl-0 = <&pcie_pins>;
pinctrl-names = "default";
- perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>;
+ perst-gpios = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>;
};
qcom,ssbi@500000 {
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
index 7a337dc08741..872f64a12047 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
@@ -100,7 +100,7 @@ m25p80@0 {
pci@40000000 {
status = "okay";
- perst-gpio = <&tlmm 38 0x1>;
+ perst-gpios = <&tlmm 38 0x1>;
};
qpic-nand@79b0000 {
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
index 06f9f2cb2fe9..ab1835b0fe40 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
@@ -10,7 +10,7 @@ / {
soc {
pci@40000000 {
status = "okay";
- perst-gpio = <&tlmm 38 0x1>;
+ perst-gpios = <&tlmm 38 0x1>;
};
spi@78b6000 {
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 996f4458d9fc..fa67cb6adcb8 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -842,7 +842,7 @@ pcie0: pci@1b500000 {
pinctrl-names = "default";
status = "disabled";
- perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
+ perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
};
pcie1: pci@1b700000 {
@@ -893,7 +893,7 @@ pcie1: pci@1b700000 {
pinctrl-names = "default";
status = "disabled";
- perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
+ perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
};
pcie2: pci@1b900000 {
@@ -944,7 +944,7 @@ pcie2: pci@1b900000 {
pinctrl-names = "default";
status = "disabled";
- perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
+ perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
};
nss_common: syscon@03000000 {
--
2.35.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v6 8/8] arm64: dts: qcom: replace deprecated perst-gpio with perst-gpios
2022-05-06 15:20 [PATCH v6 0/8] dt-bindings: YAMLify pci/qcom,pcie schema Dmitry Baryshkov
` (6 preceding siblings ...)
2022-05-06 15:21 ` [PATCH v6 7/8] arm: dts: qcom-*: replace deprecated perst-gpio with perst-gpios Dmitry Baryshkov
@ 2022-05-06 15:21 ` Dmitry Baryshkov
2022-05-10 16:50 ` [PATCH v6 0/8] dt-bindings: YAMLify pci/qcom,pcie schema Rob Herring
` (2 subsequent siblings)
10 siblings, 0 replies; 21+ messages in thread
From: Dmitry Baryshkov @ 2022-05-06 15:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi, Bjorn Helgaas,
Stanimir Varbanov, Manivannan Sadhasivam
Cc: Vinod Koul, linux-arm-msm, linux-pci, devicetree, Krzysztof Kozlowski
Replace deprecated perst-gpio and wake-gpio properties with up-to-date
perst-gpios and wake-gpios in the Qualcomm device trees.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 6 +++---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 4 ++--
arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4 ++--
8 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts
index f623db8451f1..9fb33850e46c 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts
@@ -497,20 +497,20 @@ config {
&pcie0 {
status = "okay";
- perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>;
+ perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&wlan_en>;
vdda-supply = <&vreg_l28a_0p925>;
};
&pcie1 {
status = "okay";
- perst-gpio = <&tlmm 130 GPIO_ACTIVE_LOW>;
+ perst-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>;
vdda-supply = <&vreg_l28a_0p925>;
};
&pcie2 {
status = "okay";
- perst-gpio = <&tlmm 114 GPIO_ACTIVE_LOW>;
+ perst-gpios = <&tlmm 114 GPIO_ACTIVE_LOW>;
vdda-supply = <&vreg_l28a_0p925>;
};
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
index b5e1eaa367bf..2d5ee337054c 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -54,12 +54,12 @@ &blsp1_uart5 {
&pcie0 {
status = "okay";
- perst-gpio = <&tlmm 61 0x1>;
+ perst-gpios = <&tlmm 61 0x1>;
};
&pcie1 {
status = "okay";
- perst-gpio = <&tlmm 58 0x1>;
+ perst-gpios = <&tlmm 58 0x1>;
};
&pcie_phy0 {
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
index 07e670829676..3c0ac747de0e 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
@@ -44,12 +44,12 @@ &blsp1_uart5 {
&pcie0 {
status = "ok";
- perst-gpio = <&tlmm 58 0x1>;
+ perst-gpios = <&tlmm 58 0x1>;
};
&pcie1 {
status = "ok";
- perst-gpio = <&tlmm 61 0x1>;
+ perst-gpios = <&tlmm 61 0x1>;
};
&pcie_phy0 {
diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi
index 3bb50cecd62d..b90000223d69 100644
--- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi
@@ -195,8 +195,8 @@ &mmcc {
&pcie0 {
status = "okay";
- perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
vddpe-3v3-supply = <&wlan_en>;
vdda-supply = <&pm8994_l28>;
};
diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
index a80c578484ba..b067b9f95189 100644
--- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
@@ -99,7 +99,7 @@ pms405_s3: s3 {
&pcie {
status = "okay";
- perst-gpio = <&tlmm 43 GPIO_ACTIVE_LOW>;
+ perst-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&perst_state>;
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
index dc17f2079695..461ba68fd939 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
@@ -362,7 +362,7 @@ &pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pcie1_clkreq_n>, <&ssd_rst_l>, <&pe_wake_odl>;
- perst-gpio = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&pp3300_ssd>;
};
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index ecbf2b89d896..8abf8077be11 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -240,7 +240,7 @@ &ipa {
&pcie1 {
status = "okay";
- perst-gpio = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&nvme_3v3_regulator>;
diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
index 28fe45c5d516..1aadd5504631 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
@@ -502,7 +502,7 @@ &mss_pil {
&pcie0 {
status = "okay";
- perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>;
+ perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
enable-gpio = <&tlmm 134 GPIO_ACTIVE_HIGH>;
vddpe-3v3-supply = <&pcie0_3p3v_dual>;
@@ -520,7 +520,7 @@ &pcie0_phy {
&pcie1 {
status = "okay";
- perst-gpio = <&tlmm 102 GPIO_ACTIVE_LOW>;
+ perst-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
--
2.35.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v6 0/8] dt-bindings: YAMLify pci/qcom,pcie schema
2022-05-06 15:20 [PATCH v6 0/8] dt-bindings: YAMLify pci/qcom,pcie schema Dmitry Baryshkov
` (7 preceding siblings ...)
2022-05-06 15:21 ` [PATCH v6 8/8] arm64: dts: qcom: " Dmitry Baryshkov
@ 2022-05-10 16:50 ` Rob Herring
2022-05-11 10:13 ` Dmitry Baryshkov
2022-05-11 14:18 ` (subset) " Lorenzo Pieralisi
2022-08-29 23:45 ` Bjorn Andersson
10 siblings, 1 reply; 21+ messages in thread
From: Rob Herring @ 2022-05-10 16:50 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Krzysztof Kozlowski, Jingoo Han,
Gustavo Pimentel, Lorenzo Pieralisi, Bjorn Helgaas,
Stanimir Varbanov, Manivannan Sadhasivam, Vinod Koul,
linux-arm-msm, linux-pci, devicetree
On Fri, May 06, 2022 at 06:20:59PM +0300, Dmitry Baryshkov wrote:
> Convert pci/qcom,pcie schema to YAML description. The first patch
> introduces several warnings which are fixed by the other patches in the
> series.
>
> Note regarding the snps,dw-pcie compatibility. The Qualcomm PCIe
> controller uses Synopsys PCIe IP core. However it is not just fused to
> the address space. Accessing PCIe registers requires several clocks and
> regulators to be powered up. Thus it can be assumed that the qcom,pcie
> bindings are not fully compatible with the snps,dw-pcie schema.
>
> Changes since v5:
> - s/stance/stanza (pointed out by Bjorn Helgaas)
>
> Changes since v4:
> - Change subjects to follow convention (suggested by Bjorn Helgaas)
>
> Changes since v3:
> - Rebase on linux-next to include sm8150 patches
>
> Changes since v2 (still kudos to Krzyshtof):
> - Readded reg-names conversion patch
> - Mention wake-gpio update in the commit message
> - Remove extra quotes in the schema
>
> Changes since v1 (all kudos to Krzyshtof):
> - Dropped the reg-names patch. It will be handled separately
> - Squashed the snps,dw-pcie removal (from schema) into the first patch
> - Replaced deprecated perst-gpio and wake-gpio with perst-gpios and
> wake-gpios in the examples and in DT files
> - Moved common clocks/clock-names, resets/reset-names and power-domains
> properties to the top level of the schema, leaving only platform
> specifics in the conditional branches
> - Dropped iommu-map/iommu-map-mask for now
> - Added (missed) interrupt-cells, clocks, clock-names, resets,
> reset-names properties to the required list (resets/reset-names are
> removed in the next patch, as they are not used on msm8996)
> - Fixed IRQ flags in the examples
> - Merged apq8064/ipq8064 into the single condition statement
> - Added extra empty lines
>
> Dmitry Baryshkov (8):
> dt-bindings: PCI: qcom: Convert to YAML
> dt-bindings: PCI: qcom: Do not require resets on msm8996 platforms
> dt-bindings: PCI: qcom: Specify reg-names explicitly
> dt-bindings: PCI: qcom: Add schema for sc7280 chipset
> arm64: dts: qcom: stop using snps,dw-pcie falback
> arm: dts: qcom: stop using snps,dw-pcie falback
> arm: dts: qcom-*: replace deprecated perst-gpio with perst-gpios
> arm64: dts: qcom: replace deprecated perst-gpio with perst-gpios
>
> .../devicetree/bindings/pci/qcom,pcie.txt | 398 ----------
> .../devicetree/bindings/pci/qcom,pcie.yaml | 714 ++++++++++++++++++
What tree do these apply to because they don't apply to rc1. I'm
assuming the PCI tree and Lorenzo should take them.
Rob
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH v6 0/8] dt-bindings: YAMLify pci/qcom,pcie schema
2022-05-10 16:50 ` [PATCH v6 0/8] dt-bindings: YAMLify pci/qcom,pcie schema Rob Herring
@ 2022-05-11 10:13 ` Dmitry Baryshkov
2022-05-11 13:09 ` Lorenzo Pieralisi
0 siblings, 1 reply; 21+ messages in thread
From: Dmitry Baryshkov @ 2022-05-11 10:13 UTC (permalink / raw)
To: Rob Herring
Cc: Andy Gross, Bjorn Andersson, Krzysztof Kozlowski, Jingoo Han,
Gustavo Pimentel, Lorenzo Pieralisi, Bjorn Helgaas,
Stanimir Varbanov, Manivannan Sadhasivam, Vinod Koul,
linux-arm-msm, linux-pci, devicetree
On Tue, 10 May 2022 at 19:50, Rob Herring <robh@kernel.org> wrote:
>
> On Fri, May 06, 2022 at 06:20:59PM +0300, Dmitry Baryshkov wrote:
> > Convert pci/qcom,pcie schema to YAML description. The first patch
> > introduces several warnings which are fixed by the other patches in the
> > series.
> >
> > Note regarding the snps,dw-pcie compatibility. The Qualcomm PCIe
> > controller uses Synopsys PCIe IP core. However it is not just fused to
> > the address space. Accessing PCIe registers requires several clocks and
> > regulators to be powered up. Thus it can be assumed that the qcom,pcie
> > bindings are not fully compatible with the snps,dw-pcie schema.
> >
> > Changes since v5:
> > - s/stance/stanza (pointed out by Bjorn Helgaas)
> >
> > Changes since v4:
> > - Change subjects to follow convention (suggested by Bjorn Helgaas)
> >
> > Changes since v3:
> > - Rebase on linux-next to include sm8150 patches
> >
> > Changes since v2 (still kudos to Krzyshtof):
> > - Readded reg-names conversion patch
> > - Mention wake-gpio update in the commit message
> > - Remove extra quotes in the schema
> >
> > Changes since v1 (all kudos to Krzyshtof):
> > - Dropped the reg-names patch. It will be handled separately
> > - Squashed the snps,dw-pcie removal (from schema) into the first patch
> > - Replaced deprecated perst-gpio and wake-gpio with perst-gpios and
> > wake-gpios in the examples and in DT files
> > - Moved common clocks/clock-names, resets/reset-names and power-domains
> > properties to the top level of the schema, leaving only platform
> > specifics in the conditional branches
> > - Dropped iommu-map/iommu-map-mask for now
> > - Added (missed) interrupt-cells, clocks, clock-names, resets,
> > reset-names properties to the required list (resets/reset-names are
> > removed in the next patch, as they are not used on msm8996)
> > - Fixed IRQ flags in the examples
> > - Merged apq8064/ipq8064 into the single condition statement
> > - Added extra empty lines
> >
> > Dmitry Baryshkov (8):
> > dt-bindings: PCI: qcom: Convert to YAML
> > dt-bindings: PCI: qcom: Do not require resets on msm8996 platforms
> > dt-bindings: PCI: qcom: Specify reg-names explicitly
> > dt-bindings: PCI: qcom: Add schema for sc7280 chipset
> > arm64: dts: qcom: stop using snps,dw-pcie falback
> > arm: dts: qcom: stop using snps,dw-pcie falback
> > arm: dts: qcom-*: replace deprecated perst-gpio with perst-gpios
> > arm64: dts: qcom: replace deprecated perst-gpio with perst-gpios
> >
> > .../devicetree/bindings/pci/qcom,pcie.txt | 398 ----------
> > .../devicetree/bindings/pci/qcom,pcie.yaml | 714 ++++++++++++++++++
>
> What tree do these apply to because they don't apply to rc1. I'm
> assuming the PCI tree and Lorenzo should take them.
The series depends on the patch in Lorenzo's tree (sm8150 bindings),
so I'd assume it would be natural to merge these patches through his
tree too.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v6 0/8] dt-bindings: YAMLify pci/qcom,pcie schema
2022-05-11 10:13 ` Dmitry Baryshkov
@ 2022-05-11 13:09 ` Lorenzo Pieralisi
2022-05-11 13:53 ` Dmitry Baryshkov
0 siblings, 1 reply; 21+ messages in thread
From: Lorenzo Pieralisi @ 2022-05-11 13:09 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Herring, Andy Gross, Bjorn Andersson, Krzysztof Kozlowski,
Jingoo Han, Gustavo Pimentel, Bjorn Helgaas, Stanimir Varbanov,
Manivannan Sadhasivam, Vinod Koul, linux-arm-msm, linux-pci,
devicetree
On Wed, May 11, 2022 at 01:13:28PM +0300, Dmitry Baryshkov wrote:
> On Tue, 10 May 2022 at 19:50, Rob Herring <robh@kernel.org> wrote:
> >
> > On Fri, May 06, 2022 at 06:20:59PM +0300, Dmitry Baryshkov wrote:
> > > Convert pci/qcom,pcie schema to YAML description. The first patch
> > > introduces several warnings which are fixed by the other patches in the
> > > series.
> > >
> > > Note regarding the snps,dw-pcie compatibility. The Qualcomm PCIe
> > > controller uses Synopsys PCIe IP core. However it is not just fused to
> > > the address space. Accessing PCIe registers requires several clocks and
> > > regulators to be powered up. Thus it can be assumed that the qcom,pcie
> > > bindings are not fully compatible with the snps,dw-pcie schema.
> > >
> > > Changes since v5:
> > > - s/stance/stanza (pointed out by Bjorn Helgaas)
> > >
> > > Changes since v4:
> > > - Change subjects to follow convention (suggested by Bjorn Helgaas)
> > >
> > > Changes since v3:
> > > - Rebase on linux-next to include sm8150 patches
> > >
> > > Changes since v2 (still kudos to Krzyshtof):
> > > - Readded reg-names conversion patch
> > > - Mention wake-gpio update in the commit message
> > > - Remove extra quotes in the schema
> > >
> > > Changes since v1 (all kudos to Krzyshtof):
> > > - Dropped the reg-names patch. It will be handled separately
> > > - Squashed the snps,dw-pcie removal (from schema) into the first patch
> > > - Replaced deprecated perst-gpio and wake-gpio with perst-gpios and
> > > wake-gpios in the examples and in DT files
> > > - Moved common clocks/clock-names, resets/reset-names and power-domains
> > > properties to the top level of the schema, leaving only platform
> > > specifics in the conditional branches
> > > - Dropped iommu-map/iommu-map-mask for now
> > > - Added (missed) interrupt-cells, clocks, clock-names, resets,
> > > reset-names properties to the required list (resets/reset-names are
> > > removed in the next patch, as they are not used on msm8996)
> > > - Fixed IRQ flags in the examples
> > > - Merged apq8064/ipq8064 into the single condition statement
> > > - Added extra empty lines
> > >
> > > Dmitry Baryshkov (8):
> > > dt-bindings: PCI: qcom: Convert to YAML
> > > dt-bindings: PCI: qcom: Do not require resets on msm8996 platforms
> > > dt-bindings: PCI: qcom: Specify reg-names explicitly
> > > dt-bindings: PCI: qcom: Add schema for sc7280 chipset
> > > arm64: dts: qcom: stop using snps,dw-pcie falback
> > > arm: dts: qcom: stop using snps,dw-pcie falback
> > > arm: dts: qcom-*: replace deprecated perst-gpio with perst-gpios
> > > arm64: dts: qcom: replace deprecated perst-gpio with perst-gpios
> > >
> > > .../devicetree/bindings/pci/qcom,pcie.txt | 398 ----------
> > > .../devicetree/bindings/pci/qcom,pcie.yaml | 714 ++++++++++++++++++
> >
> > What tree do these apply to because they don't apply to rc1. I'm
> > assuming the PCI tree and Lorenzo should take them.
>
> The series depends on the patch in Lorenzo's tree (sm8150 bindings),
> so I'd assume it would be natural to merge these patches through his
> tree too.
I can take the DT bindings but the dts updates I'd prefer if they
went via platform trees. Is that OK ?
Thanks,
Lorenzo
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v6 0/8] dt-bindings: YAMLify pci/qcom,pcie schema
2022-05-11 13:09 ` Lorenzo Pieralisi
@ 2022-05-11 13:53 ` Dmitry Baryshkov
2022-05-11 14:00 ` Lorenzo Pieralisi
0 siblings, 1 reply; 21+ messages in thread
From: Dmitry Baryshkov @ 2022-05-11 13:53 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Rob Herring, Andy Gross, Bjorn Andersson, Krzysztof Kozlowski,
Jingoo Han, Gustavo Pimentel, Bjorn Helgaas, Stanimir Varbanov,
Manivannan Sadhasivam, Vinod Koul, linux-arm-msm, linux-pci,
devicetree
On Wed, 11 May 2022 at 16:10, Lorenzo Pieralisi
<lorenzo.pieralisi@arm.com> wrote:
>
> On Wed, May 11, 2022 at 01:13:28PM +0300, Dmitry Baryshkov wrote:
> > On Tue, 10 May 2022 at 19:50, Rob Herring <robh@kernel.org> wrote:
> > >
> > > On Fri, May 06, 2022 at 06:20:59PM +0300, Dmitry Baryshkov wrote:
> > > > Convert pci/qcom,pcie schema to YAML description. The first patch
> > > > introduces several warnings which are fixed by the other patches in the
> > > > series.
> > > >
> > > > Note regarding the snps,dw-pcie compatibility. The Qualcomm PCIe
> > > > controller uses Synopsys PCIe IP core. However it is not just fused to
> > > > the address space. Accessing PCIe registers requires several clocks and
> > > > regulators to be powered up. Thus it can be assumed that the qcom,pcie
> > > > bindings are not fully compatible with the snps,dw-pcie schema.
> > > >
> > > > Changes since v5:
> > > > - s/stance/stanza (pointed out by Bjorn Helgaas)
> > > >
> > > > Changes since v4:
> > > > - Change subjects to follow convention (suggested by Bjorn Helgaas)
> > > >
> > > > Changes since v3:
> > > > - Rebase on linux-next to include sm8150 patches
> > > >
> > > > Changes since v2 (still kudos to Krzyshtof):
> > > > - Readded reg-names conversion patch
> > > > - Mention wake-gpio update in the commit message
> > > > - Remove extra quotes in the schema
> > > >
> > > > Changes since v1 (all kudos to Krzyshtof):
> > > > - Dropped the reg-names patch. It will be handled separately
> > > > - Squashed the snps,dw-pcie removal (from schema) into the first patch
> > > > - Replaced deprecated perst-gpio and wake-gpio with perst-gpios and
> > > > wake-gpios in the examples and in DT files
> > > > - Moved common clocks/clock-names, resets/reset-names and power-domains
> > > > properties to the top level of the schema, leaving only platform
> > > > specifics in the conditional branches
> > > > - Dropped iommu-map/iommu-map-mask for now
> > > > - Added (missed) interrupt-cells, clocks, clock-names, resets,
> > > > reset-names properties to the required list (resets/reset-names are
> > > > removed in the next patch, as they are not used on msm8996)
> > > > - Fixed IRQ flags in the examples
> > > > - Merged apq8064/ipq8064 into the single condition statement
> > > > - Added extra empty lines
> > > >
> > > > Dmitry Baryshkov (8):
> > > > dt-bindings: PCI: qcom: Convert to YAML
> > > > dt-bindings: PCI: qcom: Do not require resets on msm8996 platforms
> > > > dt-bindings: PCI: qcom: Specify reg-names explicitly
> > > > dt-bindings: PCI: qcom: Add schema for sc7280 chipset
> > > > arm64: dts: qcom: stop using snps,dw-pcie falback
> > > > arm: dts: qcom: stop using snps,dw-pcie falback
> > > > arm: dts: qcom-*: replace deprecated perst-gpio with perst-gpios
> > > > arm64: dts: qcom: replace deprecated perst-gpio with perst-gpios
> > > >
> > > > .../devicetree/bindings/pci/qcom,pcie.txt | 398 ----------
> > > > .../devicetree/bindings/pci/qcom,pcie.yaml | 714 ++++++++++++++++++
> > >
> > > What tree do these apply to because they don't apply to rc1. I'm
> > > assuming the PCI tree and Lorenzo should take them.
> >
> > The series depends on the patch in Lorenzo's tree (sm8150 bindings),
> > so I'd assume it would be natural to merge these patches through his
> > tree too.
>
> I can take the DT bindings but the dts updates I'd prefer if they
> went via platform trees. Is that OK ?
Yes, that's fine with me. I think Bjorn has sent 5.19 pull request
already, I'll track them getting merged into 5.19 or 5.20.
>
> Thanks,
> Lorenzo
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v6 0/8] dt-bindings: YAMLify pci/qcom,pcie schema
2022-05-11 13:53 ` Dmitry Baryshkov
@ 2022-05-11 14:00 ` Lorenzo Pieralisi
2022-05-11 14:09 ` Dmitry Baryshkov
0 siblings, 1 reply; 21+ messages in thread
From: Lorenzo Pieralisi @ 2022-05-11 14:00 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Herring, Andy Gross, Bjorn Andersson, Krzysztof Kozlowski,
Jingoo Han, Gustavo Pimentel, Bjorn Helgaas, Stanimir Varbanov,
Manivannan Sadhasivam, Vinod Koul, linux-arm-msm, linux-pci,
devicetree
On Wed, May 11, 2022 at 04:53:43PM +0300, Dmitry Baryshkov wrote:
> On Wed, 11 May 2022 at 16:10, Lorenzo Pieralisi
> <lorenzo.pieralisi@arm.com> wrote:
> >
> > On Wed, May 11, 2022 at 01:13:28PM +0300, Dmitry Baryshkov wrote:
> > > On Tue, 10 May 2022 at 19:50, Rob Herring <robh@kernel.org> wrote:
> > > >
> > > > On Fri, May 06, 2022 at 06:20:59PM +0300, Dmitry Baryshkov wrote:
> > > > > Convert pci/qcom,pcie schema to YAML description. The first patch
> > > > > introduces several warnings which are fixed by the other patches in the
> > > > > series.
> > > > >
> > > > > Note regarding the snps,dw-pcie compatibility. The Qualcomm PCIe
> > > > > controller uses Synopsys PCIe IP core. However it is not just fused to
> > > > > the address space. Accessing PCIe registers requires several clocks and
> > > > > regulators to be powered up. Thus it can be assumed that the qcom,pcie
> > > > > bindings are not fully compatible with the snps,dw-pcie schema.
> > > > >
> > > > > Changes since v5:
> > > > > - s/stance/stanza (pointed out by Bjorn Helgaas)
> > > > >
> > > > > Changes since v4:
> > > > > - Change subjects to follow convention (suggested by Bjorn Helgaas)
> > > > >
> > > > > Changes since v3:
> > > > > - Rebase on linux-next to include sm8150 patches
> > > > >
> > > > > Changes since v2 (still kudos to Krzyshtof):
> > > > > - Readded reg-names conversion patch
> > > > > - Mention wake-gpio update in the commit message
> > > > > - Remove extra quotes in the schema
> > > > >
> > > > > Changes since v1 (all kudos to Krzyshtof):
> > > > > - Dropped the reg-names patch. It will be handled separately
> > > > > - Squashed the snps,dw-pcie removal (from schema) into the first patch
> > > > > - Replaced deprecated perst-gpio and wake-gpio with perst-gpios and
> > > > > wake-gpios in the examples and in DT files
> > > > > - Moved common clocks/clock-names, resets/reset-names and power-domains
> > > > > properties to the top level of the schema, leaving only platform
> > > > > specifics in the conditional branches
> > > > > - Dropped iommu-map/iommu-map-mask for now
> > > > > - Added (missed) interrupt-cells, clocks, clock-names, resets,
> > > > > reset-names properties to the required list (resets/reset-names are
> > > > > removed in the next patch, as they are not used on msm8996)
> > > > > - Fixed IRQ flags in the examples
> > > > > - Merged apq8064/ipq8064 into the single condition statement
> > > > > - Added extra empty lines
> > > > >
> > > > > Dmitry Baryshkov (8):
> > > > > dt-bindings: PCI: qcom: Convert to YAML
> > > > > dt-bindings: PCI: qcom: Do not require resets on msm8996 platforms
> > > > > dt-bindings: PCI: qcom: Specify reg-names explicitly
> > > > > dt-bindings: PCI: qcom: Add schema for sc7280 chipset
> > > > > arm64: dts: qcom: stop using snps,dw-pcie falback
> > > > > arm: dts: qcom: stop using snps,dw-pcie falback
> > > > > arm: dts: qcom-*: replace deprecated perst-gpio with perst-gpios
> > > > > arm64: dts: qcom: replace deprecated perst-gpio with perst-gpios
> > > > >
> > > > > .../devicetree/bindings/pci/qcom,pcie.txt | 398 ----------
> > > > > .../devicetree/bindings/pci/qcom,pcie.yaml | 714 ++++++++++++++++++
> > > >
> > > > What tree do these apply to because they don't apply to rc1. I'm
> > > > assuming the PCI tree and Lorenzo should take them.
> > >
> > > The series depends on the patch in Lorenzo's tree (sm8150 bindings),
> > > so I'd assume it would be natural to merge these patches through his
> > > tree too.
> >
> > I can take the DT bindings but the dts updates I'd prefer if they
> > went via platform trees. Is that OK ?
>
> Yes, that's fine with me. I think Bjorn has sent 5.19 pull request
> already, I'll track them getting merged into 5.19 or 5.20.
I assume you meant BjornA sent a PR with patches [5-8] in it,
correct ?
I will only pull the DT bindings, patches [1-4], please let me
know if that's what you expect.
Lorenzo
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v6 0/8] dt-bindings: YAMLify pci/qcom,pcie schema
2022-05-11 14:00 ` Lorenzo Pieralisi
@ 2022-05-11 14:09 ` Dmitry Baryshkov
0 siblings, 0 replies; 21+ messages in thread
From: Dmitry Baryshkov @ 2022-05-11 14:09 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Rob Herring, Andy Gross, Bjorn Andersson, Krzysztof Kozlowski,
Jingoo Han, Gustavo Pimentel, Bjorn Helgaas, Stanimir Varbanov,
Manivannan Sadhasivam, Vinod Koul, linux-arm-msm, linux-pci,
devicetree
On Wed, 11 May 2022 at 17:00, Lorenzo Pieralisi
<lorenzo.pieralisi@arm.com> wrote:
>
> On Wed, May 11, 2022 at 04:53:43PM +0300, Dmitry Baryshkov wrote:
> > On Wed, 11 May 2022 at 16:10, Lorenzo Pieralisi
> > <lorenzo.pieralisi@arm.com> wrote:
> > >
> > > On Wed, May 11, 2022 at 01:13:28PM +0300, Dmitry Baryshkov wrote:
> > > > On Tue, 10 May 2022 at 19:50, Rob Herring <robh@kernel.org> wrote:
> > > > >
> > > > > On Fri, May 06, 2022 at 06:20:59PM +0300, Dmitry Baryshkov wrote:
> > > > > > Convert pci/qcom,pcie schema to YAML description. The first patch
> > > > > > introduces several warnings which are fixed by the other patches in the
> > > > > > series.
> > > > > >
> > > > > > Note regarding the snps,dw-pcie compatibility. The Qualcomm PCIe
> > > > > > controller uses Synopsys PCIe IP core. However it is not just fused to
> > > > > > the address space. Accessing PCIe registers requires several clocks and
> > > > > > regulators to be powered up. Thus it can be assumed that the qcom,pcie
> > > > > > bindings are not fully compatible with the snps,dw-pcie schema.
> > > > > >
> > > > > > Changes since v5:
> > > > > > - s/stance/stanza (pointed out by Bjorn Helgaas)
> > > > > >
> > > > > > Changes since v4:
> > > > > > - Change subjects to follow convention (suggested by Bjorn Helgaas)
> > > > > >
> > > > > > Changes since v3:
> > > > > > - Rebase on linux-next to include sm8150 patches
> > > > > >
> > > > > > Changes since v2 (still kudos to Krzyshtof):
> > > > > > - Readded reg-names conversion patch
> > > > > > - Mention wake-gpio update in the commit message
> > > > > > - Remove extra quotes in the schema
> > > > > >
> > > > > > Changes since v1 (all kudos to Krzyshtof):
> > > > > > - Dropped the reg-names patch. It will be handled separately
> > > > > > - Squashed the snps,dw-pcie removal (from schema) into the first patch
> > > > > > - Replaced deprecated perst-gpio and wake-gpio with perst-gpios and
> > > > > > wake-gpios in the examples and in DT files
> > > > > > - Moved common clocks/clock-names, resets/reset-names and power-domains
> > > > > > properties to the top level of the schema, leaving only platform
> > > > > > specifics in the conditional branches
> > > > > > - Dropped iommu-map/iommu-map-mask for now
> > > > > > - Added (missed) interrupt-cells, clocks, clock-names, resets,
> > > > > > reset-names properties to the required list (resets/reset-names are
> > > > > > removed in the next patch, as they are not used on msm8996)
> > > > > > - Fixed IRQ flags in the examples
> > > > > > - Merged apq8064/ipq8064 into the single condition statement
> > > > > > - Added extra empty lines
> > > > > >
> > > > > > Dmitry Baryshkov (8):
> > > > > > dt-bindings: PCI: qcom: Convert to YAML
> > > > > > dt-bindings: PCI: qcom: Do not require resets on msm8996 platforms
> > > > > > dt-bindings: PCI: qcom: Specify reg-names explicitly
> > > > > > dt-bindings: PCI: qcom: Add schema for sc7280 chipset
> > > > > > arm64: dts: qcom: stop using snps,dw-pcie falback
> > > > > > arm: dts: qcom: stop using snps,dw-pcie falback
> > > > > > arm: dts: qcom-*: replace deprecated perst-gpio with perst-gpios
> > > > > > arm64: dts: qcom: replace deprecated perst-gpio with perst-gpios
> > > > > >
> > > > > > .../devicetree/bindings/pci/qcom,pcie.txt | 398 ----------
> > > > > > .../devicetree/bindings/pci/qcom,pcie.yaml | 714 ++++++++++++++++++
> > > > >
> > > > > What tree do these apply to because they don't apply to rc1. I'm
> > > > > assuming the PCI tree and Lorenzo should take them.
> > > >
> > > > The series depends on the patch in Lorenzo's tree (sm8150 bindings),
> > > > so I'd assume it would be natural to merge these patches through his
> > > > tree too.
> > >
> > > I can take the DT bindings but the dts updates I'd prefer if they
> > > went via platform trees. Is that OK ?
> >
> > Yes, that's fine with me. I think Bjorn has sent 5.19 pull request
> > already, I'll track them getting merged into 5.19 or 5.20.
>
> I assume you meant BjornA sent a PR with patches [5-8] in it,
> correct ?
>
> I will only pull the DT bindings, patches [1-4], please let me
> know if that's what you expect.
Yes and Yes.
>
> Lorenzo
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: (subset) [PATCH v6 0/8] dt-bindings: YAMLify pci/qcom,pcie schema
2022-05-06 15:20 [PATCH v6 0/8] dt-bindings: YAMLify pci/qcom,pcie schema Dmitry Baryshkov
` (8 preceding siblings ...)
2022-05-10 16:50 ` [PATCH v6 0/8] dt-bindings: YAMLify pci/qcom,pcie schema Rob Herring
@ 2022-05-11 14:18 ` Lorenzo Pieralisi
2022-08-29 23:45 ` Bjorn Andersson
10 siblings, 0 replies; 21+ messages in thread
From: Lorenzo Pieralisi @ 2022-05-11 14:18 UTC (permalink / raw)
To: Manivannan Sadhasivam, Dmitry Baryshkov, Rob Herring,
Stanimir Varbanov, Gustavo Pimentel, Bjorn Helgaas, Jingoo Han,
Andy Gross, Bjorn Andersson, Krzysztof Kozlowski
Cc: Lorenzo Pieralisi, Vinod Koul, devicetree, linux-arm-msm, linux-pci
On Fri, 6 May 2022 18:20:59 +0300, Dmitry Baryshkov wrote:
> Convert pci/qcom,pcie schema to YAML description. The first patch
> introduces several warnings which are fixed by the other patches in the
> series.
>
> Note regarding the snps,dw-pcie compatibility. The Qualcomm PCIe
> controller uses Synopsys PCIe IP core. However it is not just fused to
> the address space. Accessing PCIe registers requires several clocks and
> regulators to be powered up. Thus it can be assumed that the qcom,pcie
> bindings are not fully compatible with the snps,dw-pcie schema.
>
> [...]
Applied to pci/qcom, thanks!
[1/8] dt-bindings: PCI: qcom: Convert to YAML
https://git.kernel.org/lpieralisi/pci/c/5383d16f06
[2/8] dt-bindings: PCI: qcom: Do not require resets on msm8996 platforms
https://git.kernel.org/lpieralisi/pci/c/81dab110d3
[3/8] dt-bindings: PCI: qcom: Specify reg-names explicitly
https://git.kernel.org/lpieralisi/pci/c/a6f2d6b1b3
[4/8] dt-bindings: PCI: qcom: Add schema for sc7280 chipset
https://git.kernel.org/lpieralisi/pci/c/bddedfeb13
Thanks,
Lorenzo
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: (subset) [PATCH v6 0/8] dt-bindings: YAMLify pci/qcom,pcie schema
2022-05-06 15:20 [PATCH v6 0/8] dt-bindings: YAMLify pci/qcom,pcie schema Dmitry Baryshkov
` (9 preceding siblings ...)
2022-05-11 14:18 ` (subset) " Lorenzo Pieralisi
@ 2022-08-29 23:45 ` Bjorn Andersson
10 siblings, 0 replies; 21+ messages in thread
From: Bjorn Andersson @ 2022-08-29 23:45 UTC (permalink / raw)
To: svarbanov, bhelgaas, Manivannan Sadhasivam, dmitry.baryshkov,
Bjorn Andersson, robh+dt, Lorenzo Pieralisi, krzk,
gustavo.pimentel, agross, jingoohan1
Cc: vkoul, linux-arm-msm, linux-pci, devicetree
On Fri, 6 May 2022 18:20:59 +0300, Dmitry Baryshkov wrote:
> Convert pci/qcom,pcie schema to YAML description. The first patch
> introduces several warnings which are fixed by the other patches in the
> series.
>
> Note regarding the snps,dw-pcie compatibility. The Qualcomm PCIe
> controller uses Synopsys PCIe IP core. However it is not just fused to
> the address space. Accessing PCIe registers requires several clocks and
> regulators to be powered up. Thus it can be assumed that the qcom,pcie
> bindings are not fully compatible with the snps,dw-pcie schema.
>
> [...]
Applied, thanks!
[5/8] arm64: dts: qcom: stop using snps,dw-pcie falback
commit: 3e4fec3bc8f8d1366cf2d8d8a054ed37e5a41cba
[8/8] arm64: dts: qcom: replace deprecated perst-gpio with perst-gpios
commit: f3f5fb3184ec0cd7f98267a8dc1c0538575fbb77
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 21+ messages in thread