From: Huacai Chen <chenhuacai@gmail.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: "Jianmin Lv" <lvjianmin@loongson.cn>,
"Huacai Chen" <chenhuacai@loongson.cn>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
linux-pci <linux-pci@vger.kernel.org>,
"Xuefeng Li" <lixuefeng@loongson.cn>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>
Subject: Re: [PATCH V16 7/7] PCI: Add quirk for multifunction devices of LS7A
Date: Fri, 22 Jul 2022 12:11:18 +0800 [thread overview]
Message-ID: <CAAhV-H6XimeV1yf3LpQrixUu-rhSM=j02XKxF=+GtNDV4MESOQ@mail.gmail.com> (raw)
In-Reply-To: <20220721175048.GA1738677@bhelgaas>
Hi, Bjorn,
On Fri, Jul 22, 2022 at 1:50 AM Bjorn Helgaas <helgaas@kernel.org> wrote:
>
> On Thu, Jul 21, 2022 at 12:47:18PM +0800, Huacai Chen wrote:
>
> > Unfortunately, this patch only lists devices in LS7A1000, but some of
> > LS7A2000 (GNET and HDMI) also need to quirk, can they be squashed in
> > this patch? If not, we will add them in a new patch.
> >
> > #define DEV_LS7A_CONF 0x7a10
> > #define DEV_LS7A_LPC 0x7a0c
> > #define DEV_LS7A_GMAC 0x7a03
> > +#define DEV_LS7A_GNET 0x7a13
> > #define DEV_LS7A_DC1 0x7a06
> > #define DEV_LS7A_DC2 0x7a36
> > #define DEV_LS7A_GPU 0x7a15
> > #define DEV_LS7A_AHCI 0x7a08
> > #define DEV_LS7A_EHCI 0x7a14
> > #define DEV_LS7A_OHCI 0x7a24
> > +#define DEV_LS7A_HDMI 0x7a37
>
> I squashed these in. Let me know if I did anything wrong:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git/commit/?id=930c6074d7dd
The logic is surely correct. But what is the principle of device list
order? If the order is value ascending, then LPC should be after AHCI;
if not, I prefer to group them with functions as below. :)
---
diff --git a/drivers/pci/controller/pci-loongson.c
b/drivers/pci/controller/pci-loongson.c
index 05997b51c86d..a7c3d5db3be8 100644
--- a/drivers/pci/controller/pci-loongson.c
+++ b/drivers/pci/controller/pci-loongson.c
@@ -22,6 +22,13 @@
#define DEV_LS2K_APB 0x7a02
#define DEV_LS7A_CONF 0x7a10
#define DEV_LS7A_LPC 0x7a0c
+#define DEV_LS7A_DC1 0x7a06
+#define DEV_LS7A_DC2 0x7a36
+#define DEV_LS7A_HDMI 0x7a37
+#define DEV_LS7A_AHCI 0x7a08
+#define DEV_LS7A_EHCI 0x7a14
+#define DEV_LS7A_GMAC 0x7a03
+#define DEV_LS7A_GNET 0x7a13
#define FLAG_CFG0 BIT(0)
#define FLAG_CFG1 BIT(1)
@@ -103,6 +110,25 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
DEV_PCIE_PORT_2, loongson_bmaster_quirk);
+static void loongson_pci_pin_quirk(struct pci_dev *pdev)
+{
+ pdev->pin = 1 + (PCI_FUNC(pdev->devfn) & 3);
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
+ DEV_LS7A_DC1, loongson_pci_pin_quirk);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
+ DEV_LS7A_DC2, loongson_pci_pin_quirk);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
+ DEV_LS7A_HDMI, loongson_pci_pin_quirk);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
+ DEV_LS7A_AHCI, loongson_pci_pin_quirk);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
+ DEV_LS7A_EHCI, loongson_pci_pin_quirk);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
+ DEV_LS7A_GMAC, loongson_pci_pin_quirk);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
+ DEV_LS7A_GNET, loongson_pci_pin_quirk);
+
static struct loongson_pci *pci_bus_to_loongson_pci(struct pci_bus *bus)
{
struct pci_config_window *cfg;
---
Huacai
next prev parent reply other threads:[~2022-07-22 4:11 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-14 12:42 [PATCH V16 0/7] PCI: Loongson pci improvements and quirks Huacai Chen
2022-07-14 12:42 ` [PATCH V16 1/7] PCI/ACPI: Guard ARM64-specific mcfg_quirks Huacai Chen
2022-07-14 12:42 ` [PATCH V16 2/7] PCI: loongson: Use generic 8/16/32-bit config ops on LS2K/LS7A Huacai Chen
2022-07-14 12:42 ` [PATCH V16 3/7] PCI: loongson: Add ACPI init support Huacai Chen
2022-07-14 12:42 ` [PATCH V16 4/7] PCI: loongson: Don't access non-existant devices Huacai Chen
2022-07-14 12:42 ` [PATCH V16 5/7] PCI: loongson: Improve the MRRS quirk for LS7A Huacai Chen
2022-07-16 7:13 ` Jianmin Lv
2022-07-16 7:31 ` Huacai Chen
2022-07-14 12:42 ` [PATCH V16 6/7] PCI: Add quirk for LS7A to avoid reboot failure Huacai Chen
2022-07-14 12:42 ` [PATCH V16 7/7] PCI: Add quirk for multifunction devices of LS7A Huacai Chen
2022-07-15 3:44 ` Bjorn Helgaas
2022-07-15 8:05 ` Jianmin Lv
2022-07-15 16:37 ` Bjorn Helgaas
2022-07-16 2:27 ` Jianmin Lv
2022-07-16 3:23 ` Bjorn Helgaas
2022-07-16 6:12 ` Jianmin Lv
2022-07-16 7:35 ` Jianmin Lv
2022-07-16 8:37 ` Huacai Chen
2022-07-16 23:32 ` Bjorn Helgaas
2022-07-17 1:41 ` Jianmin Lv
2022-07-17 14:11 ` Huacai Chen
2022-07-18 17:00 ` Bjorn Helgaas
2022-07-21 4:47 ` Huacai Chen
2022-07-21 17:50 ` Bjorn Helgaas
2022-07-22 4:11 ` Huacai Chen [this message]
2022-07-15 22:18 ` [PATCH V16 0/7] PCI: Loongson pci improvements and quirks Bjorn Helgaas
2022-07-16 9:54 ` Huacai Chen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAAhV-H6XimeV1yf3LpQrixUu-rhSM=j02XKxF=+GtNDV4MESOQ@mail.gmail.com' \
--to=chenhuacai@gmail.com \
--cc=bhelgaas@google.com \
--cc=chenhuacai@loongson.cn \
--cc=helgaas@kernel.org \
--cc=jiaxun.yang@flygoat.com \
--cc=kw@linux.com \
--cc=linux-pci@vger.kernel.org \
--cc=lixuefeng@loongson.cn \
--cc=lorenzo.pieralisi@arm.com \
--cc=lvjianmin@loongson.cn \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).