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[209.85.167.181]) by smtp.gmail.com with ESMTPSA id q5sm312248oia.21.2020.02.10.10.42.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 10 Feb 2020 10:42:00 -0800 (PST) Received: by mail-oi1-f181.google.com with SMTP id j132so10161980oih.9; Mon, 10 Feb 2020 10:42:00 -0800 (PST) X-Received: by 2002:aca:3f8b:: with SMTP id m133mr269681oia.51.1581360120170; Mon, 10 Feb 2020 10:42:00 -0800 (PST) MIME-Version: 1.0 References: <20191120034451.30102-1-Zhiqiang.Hou@nxp.com> <20200110153347.GA29372@e121166-lin.cambridge.arm.com> <20200210152257.GD25745@shell.armlinux.org.uk> In-Reply-To: From: Li Yang Date: Mon, 10 Feb 2020 12:41:49 -0600 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCHv9 00/12] PCI: Recode Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs To: Olof Johansson , Laurentiu Tudor Cc: Russell King - ARM Linux admin , "Z.q. Hou" , "bhelgaas@google.com" , "mark.rutland@arm.com" , "devicetree@vger.kernel.org" , Lorenzo Pieralisi , "m.karthikeyan@mobiveil.co.in" , "arnd@arndb.de" , "linux-pci@vger.kernel.org" , "l.subrahmanya@mobiveil.co.in" , "will.deacon@arm.com" , "linux-kernel@vger.kernel.org" , "M.h. Lian" , "robh+dt@kernel.org" , Mingkai Hu , "catalin.marinas@arm.com" , Xiaowei Bao , "andrew.murray@arm.com" , "shawnguo@kernel.org" , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="UTF-8" Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Mon, Feb 10, 2020 at 9:32 AM Olof Johansson wrote: > > On Mon, Feb 10, 2020 at 4:23 PM Russell King - ARM Linux admin > wrote: > > > > On Mon, Feb 10, 2020 at 04:12:30PM +0100, Olof Johansson wrote: > > > On Thu, Feb 6, 2020 at 11:57 AM Z.q. Hou wrote: > > > > > > > > Hi Olof, > > > > > > > > Thanks a lot for your comments! > > > > And sorry for my delay respond! > > > > > > Actually, they apply with only minor conflicts on top of current -next. > > > > > > Bjorn, any chance we can get you to pick these up pretty soon? They > > > enable full use of a promising ARM developer system, the SolidRun > > > HoneyComb, and would be quite valuable for me and others to be able to > > > use with mainline or -next without any additional patches applied -- > > > which this patchset achieves. > > > > > > I know there are pending revisions based on feedback. I'll leave it up > > > to you and others to determine if that can be done with incremental > > > patches on top, or if it should be fixed before the initial patchset > > > is applied. But all in all, it's holding up adaption by me and surely > > > others of a very interesting platform -- I'm looking to replace my > > > aging MacchiatoBin with one of these and would need PCIe/NVMe to work > > > before I do. > > > > If you're going to be using NVMe, make sure you use a power-fail safe > > version; I've already had one instance where ext4 failed to mount > > because of a corrupted journal using an XPG SX8200 after the Honeycomb > > Serror'd, and then I powered it down after a few hours before later > > booting it back up. > > > > EXT4-fs (nvme0n1p2): INFO: recovery required on readonly filesystem > > EXT4-fs (nvme0n1p2): write access will be enabled during recovery > > JBD2: journal transaction 80849 on nvme0n1p2-8 is corrupt. > > EXT4-fs (nvme0n1p2): error loading journal > > Hmm, using btrfs on mine, not sure if the exposure is similar or not. > > Do you know if the SErr was due to a known issue and/or if it's > something that's fixed in production silicon? > > (I still can't enable SMMU since across a warm reboot it fails > *completely*, with nothing coming up and working. NXP folks, you > listening? :) This is a known issue about DPAA2 MC bus not working well with SMMU based IO mapping. Adding Laurentiu to the chain who has been looking into this issue. Regards, Leo