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From: Bjorn Helgaas <bhelgaas@google.com>
To: Sasha Levin <sashal@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	x86@kernel.org, linux-pci@vger.kernel.org,
	stable@vger.kernel.org
Subject: Re: [PATCH v2] PCI: Fixup the RTIT_BAR of Intel TH on Denverton
Date: Mon, 11 Feb 2019 14:20:23 -0600	[thread overview]
Message-ID: <CAErSpo5+vJ=zB0epJ7U9KWUCNnCH-wxyiTu022C-AaRh5R0NnA@mail.gmail.com> (raw)
In-Reply-To: <20190211172611.505A2222A2@mail.kernel.org>

On Mon, Feb 11, 2019 at 11:26 AM Sasha Levin <sashal@kernel.org> wrote:
>
> Hi,
>
> [This is an automated email]
>
> This commit has been processed because it contains a "Fixes:" tag,
> fixing commit: 5118ccd34780 intel_th: pci: Add Denverton SOC support.
>
> The bot has tested the following trees: v4.20.7, v4.19.20, v4.14.98.
>
> v4.20.7: Build OK!
> v4.19.20: Build OK!
> v4.14.98: Failed to apply! Possible dependencies:
>     fa564ad96366 ("x86/PCI: Enable a 64bit BAR on AMD Family 15h (Models 00-1f, 30-3f, 60-7f)")
>
>
> How should we proceed with this patch?

This patch should be applied to all stable kernels.  There is no
dependency on any other patch.  There will be trivial conflicts on
kernels older than v4.15, but those are easy to resolve.

Bjorn

      parent reply	other threads:[~2019-02-11 20:20 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-07 13:30 [PATCH v2] PCI: Fixup the RTIT_BAR of Intel TH on Denverton Alexander Shishkin
2019-02-07 15:02 ` Bjorn Helgaas
2019-02-11  7:41 ` Ingo Molnar
2019-02-11 14:42   ` Bjorn Helgaas
     [not found] ` <20190211172611.505A2222A2@mail.kernel.org>
2019-02-11 20:20   ` Bjorn Helgaas [this message]

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