From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-gg0-f174.google.com ([209.85.161.174]:56511 "EHLO mail-gg0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750768Ab2HNE0R (ORCPT ); Tue, 14 Aug 2012 00:26:17 -0400 Received: by ggdk6 with SMTP id k6so4107175ggd.19 for ; Mon, 13 Aug 2012 21:26:16 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1343836477-7287-1-git-send-email-jiang.liu@huawei.com> References: <1343836477-7287-1-git-send-email-jiang.liu@huawei.com> From: Bjorn Helgaas Date: Mon, 13 Aug 2012 21:25:55 -0700 Message-ID: Subject: Re: [PATCH v3 00/32] provide interfaces to access PCIe capabilities registers To: Jiang Liu Cc: Don Dutile , Yinghai Lu , Taku Izumi , "Rafael J . Wysocki" , Kenji Kaneshige , Yijing Wang , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 Sender: linux-pci-owner@vger.kernel.org List-ID: On Wed, Aug 1, 2012 at 8:54 AM, Jiang Liu wrote: > From: Jiang Liu > > As suggested by Bjorn Helgaas and Don Dutile in threads > http://www.spinics.net/lists/linux-pci/msg15663.html, we could improve access > to PCIe capabilities register in to way: > 1) cache content of PCIe Capabilities Register into struct pce_dev to avoid > repeatedly reading this register because it's read only. > 2) provide access functions for PCIe Capabilities registers to hide differences > among PCIe base specifications, so the caller don't need to handle those > differences. > > This patch set applies to > git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git pci-next Would you mind rebasing this to v3.6-rc1? I think you posted this when my branch was still 3.5-based, and there are some upstream changes that cause minor conflicts here. You currently have: int pci_pcie_capability_change_word(struct pci_dev *dev, int pos, u16 set_bits, u16 clear_bits) I think this is a bit awkward because the function name doesn't suggest *how* the word will be changed, and the clearing happens before the setting (opposite the parameter order). Something like: int pci_pcie_capability_mask_and_set_word(..., u16 mask, u16 set) or int pci_pcie_capability_clear_and_set_word(..., u16 clear, u16 set) would be more obvious. If you use "mask_and_set", I think the function should do "(val & mask) | set" with the complement being at the call site. If you use "clear_and_set", I think it's OK to do "(val & ~mask) | set" as in your current patch. I know I suggested the "pci_pcie_capability_*" names, but they're getting a bit unwieldy, especially if we do "mask_and_set" or similar. There are already several "pcie_*" functions, so maybe we should drop the leading "pci_" from these and just have: pcie_capability_read_word pcie_capability_write_word pcie_capability_mask_and_set_word Bjorn